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    Structure and method to form source and drain regions over doped depletion regions
    1.
    发明申请
    Structure and method to form source and drain regions over doped depletion regions 有权
    在掺杂耗尽区上形成源极和漏极区的结构和方法

    公开(公告)号：US20070178652A1

    公开(公告)日：2007-08-02

    申请号：US11706891

    申请日：2007-02-14

    申请人： King Chui ,  Francis Benistant ,  Ganesh Samudra ,  Kian Tee ,  Yisuo Li ,  Kum Woh Leong ,  Kheng Tee

    发明人： King Chui ,  Francis Benistant ,  Ganesh Samudra ,  Kian Tee ,  Yisuo Li ,  Kum Woh Leong ,  Kheng Tee

    IPC分类号： H01L21/336 ,  H01L21/265 ,  H01L21/425

    CPC分类号： H01L29/0847 ,  H01L21/823878 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  Y10S438/961

    摘要： A structure and method of reducing junction capacitance of a source/drain region in a transistor. A gate structure is formed over on a first conductive type substrate. We perform a doped depletion region implantation by implanting ions being the second conductive type to the substrate using the gate structure as a mask, to form a doped depletion region beneath and separated from the source/drain regions. The doped depletion regions have an impurity concentration and thickness so that the doped depletion regions are depleted due to a built-in potential creatable between the doped depletion regions and the substrate. The doped depletion region and substrate form depletion regions between the source/drain regions and the doped depletion region. We perform a S/D implant by implanting ions having a second conductivity type into the substrate to form S/D regions. The doped depletion region and depletion regions reduce the capacitance between the source/drain regions and the substrate.

    摘要翻译： 减小晶体管中源/漏区的结电容的结构和方法。 栅极结构形成在第一导电类型的衬底上。 我们通过使用栅极结构作为掩模将作为第二导电类型的离子注入到衬底来进行掺杂耗尽区域注入，以在源极/漏极区域之下形成掺杂的耗尽区域并从源极/漏极区域分离。 掺杂的耗尽区具有杂质浓度和厚度，使得掺杂的耗尽区由于在掺杂耗尽区和衬底之间可建立的内置势而耗尽。 掺杂耗尽区和衬底在源/漏区和掺杂耗尽区之间形成耗尽区。 我们通过将具有第二导电类型的离子注入到衬底中来形成S / D区域来进行S / D植入。 掺杂的耗尽区域和耗尽区域减小了源/漏区域和衬底之间的电容。

    Structure and method to form source and drain regions over doped depletion regions
    2.
    发明申请
    Structure and method to form source and drain regions over doped depletion regions 有权
    在掺杂耗尽区上形成源极和漏极区的结构和方法

    公开(公告)号：US20050156253A1

    公开(公告)日：2005-07-21

    申请号：US10761613

    申请日：2004-01-21

    申请人： King Chui ,  Francis Benistant ,  Ganesh Samudra ,  Kian Tee ,  Yisuo Li ,  Kum Leong ,  Kheng Tee

    发明人： King Chui ,  Francis Benistant ,  Ganesh Samudra ,  Kian Tee ,  Yisuo Li ,  Kum Leong ,  Kheng Tee

    IPC分类号： H01L21/336 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/76 ,  H01L29/78

    CPC分类号： H01L29/0847 ,  H01L21/823878 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833 ,  Y10S438/961

    摘要： A structure and method of reducing junction capacitance of a source/drain region in a transistor. A gate structure is formed over on a first conductive type substrate. We perform a doped depletion region implantation by implanting ions being the second conductive type to the substrate using the gate structure as a mask, to form a doped depletion region beneath and separated from the source/drain regions. The doped depletion regions have an impurity concentration and thickness so that the doped depletion regions are depleted due to a built-in potential creatable between the doped depletion regions and the substrate. The doped depletion region and substrate form depletion regions between the source/drain regions and the doped depletion region. We perform a S/D implant by implanting ions having a second conductivity type into the substrate to form S/D regions. The doped depletion region and depletion regions reduce the capacitance between the source/drain regions and the substrate.

    摘要翻译： 减小晶体管中源/漏区的结电容的结构和方法。 栅极结构形成在第一导电类型的衬底上。 我们通过使用栅极结构作为掩模将作为第二导电类型的离子注入到衬底来进行掺杂耗尽区域注入，以在源极/漏极区域之下形成掺杂的耗尽区域并从源极/漏极区域分离。 掺杂耗尽区具有杂质浓度和厚度，使得掺杂的耗尽区由于在掺杂的耗尽区和衬底之间可建立的内置势而耗尽。 掺杂耗尽区和衬底在源/漏区和掺杂耗尽区之间形成耗尽区。 我们通过将具有第二导电类型的离子注入到衬底中来形成S / D区域来进行S / D植入。 掺杂的耗尽区域和耗尽区域减小了源/漏区域和衬底之间的电容。

    Selective oxide trimming to improve metal T-gate transistor
    4.
    发明申请
    Selective oxide trimming to improve metal T-gate transistor 有权
    选择性氧化物修整以改善金属T型栅极晶体管

    公开(公告)号：US20060008973A1

    公开(公告)日：2006-01-12

    申请号：US10885855

    申请日：2004-07-07

    申请人： Timothy Phua ,  Kheng Tee ,  Liang Hsia

    发明人： Timothy Phua ,  Kheng Tee ,  Liang Hsia

    IPC分类号： H01L21/336 ,  H01L21/8238

    CPC分类号： H01L29/6653 ,  H01L21/26586 ,  H01L21/28079 ,  H01L21/28123 ,  H01L21/823842 ,  H01L21/82385 ,  H01L21/823857 ,  H01L29/495 ,  H01L29/66545

    摘要： A process to form a FET using a replacement gate. An example feature is that the PMOS sacrificial gate is made narrower than the NMOS sacrificial gate. The PMOS gate is implanted preferably with Ge to increase the amount of poly sacrificial gate that is oxidized to form PMOS spacers. The spacers are used as masks for the LDD Implant. The space between the PLLD regions is preferably larger that the space between the NLDD regions because of the wider PMOS spacers. The PLDD tends to diffuse readily more than NLDD due to the dopant being small and light (i.e. Boron). The wider spacer between the PMOS regions improves device performance by improving the short channel effects for PMOS. In addition, the oxidization of the sacrificial gates allows trimming of sacrificial gates thus extending the limitation of lithography. Another feature of an embodiment is that a portion of the initial pad oxide is removed, thus reducing the amount of undercut created during the channel oxide strip for the dummy gate process. This would improve on the gate overlap capacitance for a T-gate transistor. In a second embodiment, two metal gates with different work functions are formed.

    摘要翻译： 使用替换栅极形成FET的工艺。 一个示例特征是使PMOS牺牲栅极比NMOS牺牲栅极窄。 PMOS栅极优选用Ge注入以增加被氧化形成PMOS间隔物的多晶牺牲栅极的量。 间隔件用作LDD植入物的掩模。 由于较宽的PMOS间隔物，PLLD区之间的空间优选大于NLDD区之间的空间。 由于掺杂剂小且轻（即硼），PLDD容易从NLDD扩散更多。 PMOS区域之间的较宽间隔通过改善PMOS的短沟道效应来提高器件性能。 此外，牺牲栅极的氧化允许修剪牺牲栅极，从而延长了光刻的限制。 一个实施例的另一个特征是初始衬垫氧化物的一部分被去除，从而减少了在用于虚拟栅极处理的沟道氧化物带期间产生的底切的量。 这将提高T栅极晶体管的栅极重叠电容。 在第二实施例中，形成具有不同功函数的两个金属栅极。

    Material architecture for the fabrication of low temperature transistor
    8.
    发明申请
    Material architecture for the fabrication of low temperature transistor 有权
    用于制造低温晶体管的材料结构

    公开(公告)号：US20060006427A1

    公开(公告)日：2006-01-12

    申请号：US10886442

    申请日：2004-07-07

    申请人： Chung Tan ,  Jinping Liu ,  Hyeokjae Lee ,  Kheng Tee ,  Elgin Quek

    发明人： Chung Tan ,  Jinping Liu ,  Hyeokjae Lee ,  Kheng Tee ,  Elgin Quek

    IPC分类号： H01L27/148 ,  H01L21/425

    CPC分类号： H01L29/6659 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/1054 ,  H01L29/1083

    摘要： A structure and method for forming a carbon-containing layer in at least a portion of the end of range regions of implanted PAI and/or doped regions. The C-containing layer/region getters defects from the implanted PAI region or doped region. Example embodiments show a C-containing layer under at FET. Other example embodiments show an implanted C-containing regions implanted into the EOR region of implanted doped regions, such as pocket regions, S/D regions and SDE regions. Low temperature anneals can be used because the carbon-containing layer reduces defects.

    摘要翻译： 在植入的PAI和/或掺杂区域的范围区域的末端的至少一部分中形成含碳层的结构和方法。 含C层/区域从植入的PAI区域或掺杂区域吸收缺陷。 示例性实施例示出了在FET下面的含C层。 其它示例性实施方案显示了植入到植入的掺杂区域例如口袋区域，S / D区域和SDE区域的EOR区域中的植入的含C区域。 可以使用低温退火，因为含碳层减少了缺陷。