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公开(公告)号：US07245556B1
公开(公告)日：2007-07-17
申请号：US11321217
申请日：2005-12-28
申请人： Yosi Pinto , Geoffrey S. Gongwer , Oren Honen
发明人： Yosi Pinto , Geoffrey S. Gongwer , Oren Honen
IPC分类号： G11C8/00
CPC分类号： G11C8/10 , G06F12/0246 , G06F2212/1036 , G06F2212/7211 , G11C16/349 , G11C16/3495
摘要： A memory system that incorporates methods of amplifying the lifetime of a counter made up of memory elements, such as EEPROM cells, having finite endurance. A relatively small memory made up of a number of individually accessible write segments, where, depending on the embodiment, each write segment is made up of a single memory cell or a small number of cells (e.g., a byte). A count is encoded so that it is distributed across a number of fields, each associated with one of the write segments, such that as the count is incremented only a single field (or, in the single bit embodiments, occasionally more than one field) is changed and that these changes are evenly distributed across the fields. The changed field is then written to the corresponding segment, while the other write segments are unchanged. Consequently, the number of rewrites to a given write segment is decreased, and the lifetime correspondingly increased, by a factor corresponding to the number of write segments used.
摘要翻译： 一种存储系统，其包含放大由具有有限耐久性的诸如EEPROM单元之类的存储元件构成的计数器的寿命的方法。 由多个单独访问的写入段构成的相对小的存储器，其中根据实施例，每个写入段由单个存储器单元或少量单元（例如，一个字节）组成。 计数被编码，使得其分布在多个字段中，每个字段与写入段之一相关联，使得当计数仅增加一个字段（或者在单个实施例中，偶尔地多于一个字段）时， 改变了这些变化是均匀地分布在各个领域。 然后将更改的字段写入相应的段，而其他写段不变。 因此，给定写入段的重写次数减少，并且寿命相应地增加了与所使用的写入段数相对应的因子。
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公开(公告)号：US07243275B2
公开(公告)日：2007-07-10
申请号：US11304961
申请日：2005-12-14
CPC分类号： G11C11/5635 , G11C11/5628 , G11C16/3454 , G11C16/3459 , G11C2211/5621
摘要： A “smart verify” technique, whereby multi-state memories are programmed using a verify-results-based dynamic adjustment of the multi-states verify range for sequential-state-based verify implementations, is presented. This technique can increase multi-state write speed while maintaining reliable operation within sequentially verified, multi-state memory implementations by providing “intelligent” element to minimize the number of sequential verify operations for each program/verify/lockout step of the write sequence. At the beginning of a program/verify cycle sequence only the lowest state or states are checked during the verify phase. As lower states are reached, additional higher states are added to the verify sequence and lower states can be removed.
摘要翻译： 提出了一种“智能验证”技术，其中使用基于验证结果的动态调整多状态验证范围对基于顺序状态的验证实现来编程多状态存储器。 该技术可以通过提供“智能”元件来最小化写入序列的每个程序/验证/锁定步骤的顺序验证操作的数量，从而提高多状态写入速度，同时在顺序验证的多状态存储器实现中保持可靠的操作。 在程序/验证周期序列的开始，在验证阶段只检查最低的状态或状态。 当达到较低的状态时，额外的更高的状态被添加到验证序列中，并且可以去除较低的状态。
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3.发明授权公开(公告)号：US07092292B2
公开(公告)日：2006-08-15
申请号：US10976692
申请日：2004-10-28
IPC分类号： G11C16/04
CPC分类号： G11C11/5642 , G11C16/0458 , G11C16/26
摘要： The present invention presents methods for reducing the amount of noise inherent in the reading of a non-volatile storage device by applying an episodic agitation (e.g. a time varying voltage) to some terminal(s) of the cell as part of the reading process. Various aspects of the present invention also extend to devices beyond non-volatile memories. According to one aspect of the present invention, in addition to the normal voltage levels applied to the cell as part of the reading process, a time varying voltage is applied to the cell. A set of exemplary embodiments apply a single or multiple set of alternating voltages to one or more terminals of a floating gate memory cell just prior to or during the signal integration time of a read process. In other embodiments, other reproducible external or internal agitations which are repeatable, and whose average effect (from one integration time to the next integration time) remains sufficiently constant so as to have a net noise reduction effect is applicable.
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公开(公告)号：US06678192B2
公开(公告)日：2004-01-13
申请号：US10053339
申请日：2001-11-02
IPC分类号： G11C1606
CPC分类号： G11C16/349 , G11C11/5621 , G11C11/5642 , G11C16/28 , G11C29/00
摘要： A memory system (e.g., memory card) having error management for stored levels (e.g., reference levels) used in discrimination of logic levels for data storage units providing data storage is disclosed. The stored levels can be stored in predetermined storage units (e.g., writable tracking storage units) in the memory system. The memory system is typically a non-volatile memory product or device that provides binary or multi-state data storage.
摘要翻译： 公开了一种对提供数据存储的数据存储单元的逻辑电平进行辨别的存储电平（例如参考电平）的错误管理的存储器系统（例如，存储卡）。 存储的电平可以存储在存储器系统中的预定存储单元（例如，可写跟踪存储单元）中。 存储器系统通常是提供二进制或多状态数据存储的非易失性存储器产品或设备。
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5.发明授权Configuration control in a programmable logic device using non-volatile elements 失效使用非易失性元件的可编程逻辑器件中的配置控制
公开(公告)号：US5968196A
公开(公告)日：1999-10-19
申请号：US63872
申请日：1998-04-21
申请人： Srinivas Ramamurthy , Neal Berger , James Fahey, Jr. , Geoffrey S. Gongwer , William J. Saiki , Eugene Jinglun Tam
发明人： Srinivas Ramamurthy , Neal Berger , James Fahey, Jr. , Geoffrey S. Gongwer , William J. Saiki , Eugene Jinglun Tam
IPC分类号： G01R31/28 , G01R31/3185
CPC分类号： G01R31/318533 , G01R31/318516
摘要： A boundary scan test circuit (JTAG) interface is used to provide data for a set of configuration latches within a Configuration Register. The Configuration Register is included within the JTAG structure as a Test Data Register (TDR). Each configuration bit within the Configuration Register consists of a Configuration Latch, and each configuration latch has an output used as a configuration control signal within an output logic macrocell. The configuration register's input signal is selectably provided from either a set of serially connected configuration bit non-volatile element sense latches or from the JTAG Test Data In (TDI) data pin for reconfiguration, prototyping, and testing.
摘要翻译： 边界扫描测试电路（JTAG）接口用于为配置寄存器内的一组配置锁存器提供数据。 配置寄存器作为测试数据寄存器（TDR）包含在JTAG结构内。 配置寄存器中的每个配置位由配置锁存器组成，每个配置锁存器都将输出用作输出逻辑宏单元内的配置控制信号。 配置寄存器的输入信号可从一组串行连接的配置位非易失性元件检测锁存器或JTAG测试数据输入（TDI）数据引脚中进行选择性地提供，用于重新配置，原型设计和测试。
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6.发明授权Integrated logic circuit with functionally flexible input/output macrocells 失效具有功能灵活的输入/输出宏单元的集成逻辑电路
公开(公告)号：US5231312A
公开(公告)日：1993-07-27
申请号：US850285
申请日：1992-03-12
申请人： Geoffrey S. Gongwer , Jinglun Tam , Keith H. Gudger , Joe Yu , Steven A. Sharp
发明人： Geoffrey S. Gongwer , Jinglun Tam , Keith H. Gudger , Joe Yu , Steven A. Sharp
IPC分类号： H03K19/173
CPC分类号： H03K19/1737
摘要： An integrated circuit package including a plurality of macrocells for connecting a logic circuit of the package to a plurality of external contacts of the package. At least one of the macrocells has an output driver that is enabled or disabled by a control signal for transmitting or preventing transmission of a logic signal to one of the contacts. The control signal is generated by a logic gate that receives and logically combines an individual output enable signal dedicated to that particular macrocell with a selected signal. One signal that may be selected is a regional output enable signal that is supplied to more than one macrocell. Each macrocell also has a feedback multiplexer selecting one signal to be sent to the logic circuit. Choices include a nonstored logic signal, a stored logic signal from a flip-flop register in the macrocell, a signal applied to the external contact associated with that macrocell, and a signal applied to another external contact associated with a different macrocell. A plurality of contacts are connected to feedback multiplexers in two different macrocells, and at least one contact connects in this manner to separate logic regions of the logic circuit. The flip-flop register in the macrocell has a choice of data inputs selected by another multiplexer from among at least one logic signal from the logic circuit and at least one signal applied to an external contact.
摘要翻译： 一种集成电路封装，包括用于将封装的逻辑电路连接到封装的多个外部触点的多个宏单元。 宏单元中的至少一个具有通过控制信号使能或禁用的输出驱动器，用于发送或阻止向一个触点发送逻辑信号。 控制信号由逻辑门产生，该逻辑门接收并逻辑地组合专用于该特定宏小区的单独输出使能信号与所选择的信号。 可以选择的一个信号是被提供给多个宏小区的区域输出使能信号。 每个宏单元还具有选择要发送到逻辑电路的一个信号的反馈多路复用器。 选择包括非存储逻辑信号，来自宏单元中的触发器寄存器的存储逻辑信号，施加到与该宏单元相关联的外部触点的信号，以及施加到与不同宏单元相关联的另一外部触点的信号。 多个触点连接到两个不同宏小区中的反馈多路复用器，并且至少一个触点以这种方式连接到逻辑电路的分离逻辑区。 宏单元中的触发器寄存器具有来自逻辑电路的至少一个逻辑信号和施加到外部触点的至少一个信号的另一多路复用器选择的数据输入的选择。
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公开(公告)号：US07916552B2
公开(公告)日：2011-03-29
申请号：US12763569
申请日：2010-04-20
IPC分类号： G11C16/04
CPC分类号： G11C16/26 , G11C11/5621 , G11C16/349
摘要： Tracking cells are used in a memory system to improve the read process. The tracking cells can provide an indication of the quality of the data and can be used as part of a data recovery operation if there is an error. The tracking cells provide a means to adjust the read parameters to optimum levels in order to reflect the current conditions of the memory system. Additionally, some memory systems that use multi-state memory cells will apply rotation data schemes to minimize wear. The rotation scheme can be encoded in the tracking cells based on the states of multiple tracking cells, which is decoded upon reading.
摘要翻译： 在存储器系统中使用跟踪单元来改善读取过程。 跟踪单元可以提供数据质量的指示，如果存在错误，可以将其用作数据恢复操作的一部分。 跟踪单元提供了将读取参数调整到最佳水平以便反映存储器系统的当前状况的手段。 另外，使用多状态存储器单元的一些存储器系统将应用旋转数据方案以最小化磨损。 可以基于多个跟踪单元的状态在跟踪单元中编码旋转方案，该单元在读取时被解码。
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公开(公告)号：US20100202199A1
公开(公告)日：2010-08-12
申请号：US12763569
申请日：2010-04-20
CPC分类号： G11C16/26 , G11C11/5621 , G11C16/349
摘要： Tracking cells are used in a memory system to improve the read process. The tracking cells can provide an indication of the quality of the data and can be used as part of a data recovery operation if there is an error. The tracking cells provide a means to adjust the read parameters to optimum levels in order to reflect the current conditions of the memory system. Additionally, some memory systems that use multi-state memory cells will apply rotation data schemes to minimize wear. The rotation scheme can be encoded in the tracking cells based on the states of multiple tracking cells, which is decoded upon reading.
摘要翻译： 在存储器系统中使用跟踪单元来改善读取过程。 跟踪单元可以提供数据质量的指示，如果存在错误，可以将其用作数据恢复操作的一部分。 跟踪单元提供了将读取参数调整到最佳水平以便反映存储器系统的当前状况的手段。 另外，使用多状态存储器单元的一些存储器系统将应用旋转数据方案以最小化磨损。 可以基于多个跟踪单元的状态在跟踪单元中编码旋转方案，该单元在读取时被解码。
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公开(公告)号：US07266026B2
公开(公告)日：2007-09-04
申请号：US11201007
申请日：2005-08-09
IPC分类号： G06F5/00
摘要： Methods and apparatus for transforming data into a format which may be efficiently stored in a non-volatile memory are disclosed. According to one aspect of the present invention, a method for storing information of a first data format in a memory system includes generating statistics associated with the first data format, and transforming the information from the first data format to a second data format using the statistics. Once the information is transformed into the second data format, the information is stored into a memory. Storing the information in the second data format in the memory includes storing an identifier that identifies a transformation used to transform the information to the second data format. In one embodiment, costs associated with storing the information in the second data format are less than or equal to costs associated with storing the information in the first data format.
摘要翻译： 公开了将数据转换成可以有效地存储在非易失性存储器中的格式的方法和装置。 根据本发明的一个方面，一种用于将第一数据格式的信息存储在存储器系统中的方法包括生成与第一数据格式相关联的统计信息，以及使用统计信息将信息从第一数据格式转换为第二数据格式 。 一旦信息被转换成第二数据格式，信息被存储到存储器中。 以第二数据格式存储在存储器中的信息包括存储识别用于将信息变换为第二数据格式的变换的标识符。 在一个实施例中，与以第二数据格式存储信息相关联的成本小于或等于与以第一数据格式存储信息相关联的成本。
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10.发明授权Increasing the effectiveness of error correction codes and operating multi-level memory systems by using information about the quality of the stored data 有权通过使用有关存储数据质量的信息，提高纠错码的有效性和操作多级存储器系统公开(公告)号：US06751766B2
公开(公告)日：2004-06-15
申请号：US10152137
申请日：2002-05-20
IPC分类号： G11C2900
CPC分类号： G11C16/3418 , G06F11/1012 , G06F11/1072 , G11C11/56 , G11C11/5621 , G11C16/3431 , G11C29/00 , G11C29/42 , G11C29/76 , G11C2029/0411
摘要： The quality of data stored in a memory system is assessed by different methods, and the memory system is operated according to the assessed quality. The data quality can be assessed during read operations. Subsequent use of an Error Correction Code can utilize the quality indications to detect and reconstruct the data with improved effectiveness. Alternatively, a statistics of data quality can be constructed and digital data values can be associated in a modified manner to prevent data corruption. In both cases the corrective actions can be implemented specifically on the poor quality data, according to suitably chosen schedules, and with improved effectiveness because of the knowledge provided by the quality indications. These methods can be especially useful in high-density memory systems constructed of multi-level storage memory cells.
摘要翻译： 通过不同的方法评估存储在存储器系统中的数据的质量，并且根据评估的质量操作存储器系统。 在读取操作期间可以评估数据质量。 随后使用纠错码可以利用质量指示来提高检测和重建数据的效率。 或者，可以构建数据质量的统计，并且可以以修改的方式将数字数据值相关联以防止数据损坏。 在这两种情况下，根据适当选择的时间表，纠正措施可以针对质量差的数据进行具体实施，并且由于质量指示提供的知识而提高了效率。 这些方法对于由多级存储单元构成的高密度存储器系统尤其有用。
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