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公开(公告)号：US06177708B1
公开(公告)日：2001-01-23
申请号：US09324324
申请日：1999-06-02
IPC分类号： H01L2941
CPC分类号： H01L27/1203 , H01L29/42384 , H01L29/78606 , H01L29/78618
摘要： A self-aligned SOI FET device with an “L” shaped gate structure allows an integral diode junction to be formed between the source and the body of the device. Two devices with this gate geometry can be advantageously placed side-by-side in a single rx opening that could accommodate but a single device with a “T” shaped gate structure. The devices in accordance with the teachings of this invention can be easily formed using standard prior art SOI processing steps. An aspect of this invention includes the use of these novel SOI devices with their body and source connected together in circuit applications, such as memory cell sense amplifiers, where high speed operation commends the use of SOI technology, but physical space considerations have limited their application.
摘要翻译： 具有“L”形栅极结构的自对准SOI FET器件允许在器件的源极和主体之间形成整体二极管结。 具有该栅极几何形状的两个器件可以有利地并排布置在可容纳但具有“T”形栅极结构的单个器件的单个rx开口中。 根据本发明的教导的器件可以使用标准的现有技术的SOI处理步骤容易地形成。 本发明的一个方面包括使用这些新颖的SOI器件，其主体和源极在诸如存储器单元读出放大器的电路应用中连接在一起，其中高速操作表示使用SOI技术，但是物理空间考虑限制了它们的应用 。
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公开(公告)号：US6154091A
公开(公告)日：2000-11-28
申请号：US324498
申请日：1999-06-02
IPC分类号： H01L27/12 , H01L29/423 , H01L29/786 , H01L25/00
CPC分类号： H01L29/78615 , H01L27/1203 , H01L29/4238 , H01L29/42384
摘要： A self-aligned SOI FET device with an "L" shaped gate structure allows an integral diode junction to be formed between the source and the body of the device. Two devices with this gate geometry can be advantageously placed side-by-side in a single rx opening that could accommodate but a single device with a "T" shaped gate structure. The devices in accordance with the teachings of this invention can be easily formed using standard prior art SOI processing steps. An aspect of this invention includes the use of these novel SOI devices with their body and source connected together in circuit applications, such as memory cell sense amplifiers, where high speed operation commends the use of SOI technology, but physical space considerations have limited their application.
摘要翻译： 具有“L”形栅极结构的自对准SOI FET器件允许在器件的源极和主体之间形成整体二极管结。 具有该栅极几何形状的两个器件可以有利地并排布置在可容纳但具有“T”形栅极结构的单个器件的单个rx开口中。 根据本发明的教导的器件可以使用标准的现有技术的SOI处理步骤容易地形成。 本发明的一个方面包括使用这些新颖的SOI器件，其主体和源极在诸如存储器单元读出放大器的电路应用中连接在一起，其中高速操作表示使用SOI技术，但是物理空间考虑限制了它们的应用 。
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公开(公告)号：US08237513B2
公开(公告)日：2012-08-07
申请号：US12821526
申请日：2010-06-23
CPC分类号： H03L3/00
摘要： A voltage controlled oscillator (VCO) for a phase locked loop (PLL) includes a startup oscillator, the startup oscillator comprising a first plurality of inverters; a primary oscillator, the primary oscillator comprising a second plurality of inverters, wherein a number of the second plurality of inverters is fewer than the number of the first plurality of inverters; and a control module connected to the startup oscillator and the primary oscillator. A method of operating a voltage controlled oscillator (VCO) in a phase locked loop (PLL), the VCO comprising a startup oscillator and a primary oscillator includes sending an enable signal to the startup oscillator; waiting a predetermined number of startup oscillator clock cycles; and when the predetermined number of startup oscillator clock cycles has elapsed, sending a disable signal to the startup oscillator, and sending an enable signal to the primary oscillator.
摘要翻译： 用于锁相环（PLL）的压控振荡器（VCO）包括启动振荡器，所述启动振荡器包括第一多个反相器; 主振荡器，所述主振荡器包括第二多个反相器，其中所述第二多个反相器的数量少于所述第一多个反相器的数量; 以及连接到启动振荡器和主振荡器的控制模块。 一种在锁相环（PLL）中操作压控振荡器（VCO）的方法，包括启动振荡器和主振荡器的VCO包括向启动振荡器发送使能信号; 等待预定数量的启动振荡器时钟周期; 并且当经过预定数量的启动振荡器时钟周期时，向启动振荡器发送禁止信号，并向主振荡器发送使能信号。
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公开(公告)号：US20090189591A1
公开(公告)日：2009-07-30
申请号：US12021484
申请日：2008-01-29
CPC分类号： G05F3/30
摘要： In temperature sensing circuitry PTAT (Proportional to Absolute Temperature) Voltage References are typically used. By adding a feedback circuit and a source follower into the classic design, the circuit can guarantee that the current is mirrored identically regardless of the value of power supply voltage. This added circuitry is easy to implement and is low in both power and area. The essence of this invention is that the PTAT circuit allows a large range of operation including low voltage (1 Volt) and more accurate temperature readings.
摘要翻译： 在温度感测电路PTAT（与绝对温度成比例）中，通常使用电压基准。 通过在经典设计中添加反馈电路和源极跟随器，电路可以保证电流相同，无论电源电压的值如何。 这种增加的电路容易实现，功率和面积都很小。 本发明的实质是PTAT电路允许包括低电压（1伏）和更准确的温度读数的大范围的操作。
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公开(公告)号：US07271643B2
公开(公告)日：2007-09-18
申请号：US11138102
申请日：2005-05-26
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： An electrically blowable fuse circuit having a fuse which may be placed in a condition to be blown. The circuit includes a first transistor having a body, a source, a drain, and a gate. The source is connected to one end of the fuse and the drain is connected to ground. The first transistor further includes a controllable parasitic device in its body. A second transistor is connected to the parasitic device such that when the second transistor is turned on, the parasitic device turns on the first transistor, allowing the fuse to be blown when the fuse is placed in a condition to be blown.
摘要翻译： 一种具有熔断器的可电熔熔断器电路，该保险丝可被放置在要被吹制的状态。 电路包括具有主体，源极，漏极和栅极的第一晶体管。 源极连接到保险丝的一端，漏极连接到地。 第一晶体管还包括其体内的可控寄生器件。 第二晶体管连接到寄生器件，使得当第二晶体管导通时，寄生器件接通第一晶体管，当保险丝置于待熔断状态时，允许保险丝熔断。
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公开(公告)号：US6023577A
公开(公告)日：2000-02-08
申请号：US938676
申请日：1997-09-26
CPC分类号： G06F17/5036
摘要： A method for use in electronic design models encoded into design software for use in SOI based FET logic design includes simulation of an SOI device and setting a floating body voltage to any desired value at any time during the simulation, by adding to the model an ideal voltage source, whose value is a desired body voltage, in series with an ideal current source, whose value is a constant times the voltage across itself. When the constant is zero no current can flow, and any additional components have no effect on the circuit. When the constant is non-zero, said ideal current source appears to be the same as a resistor such that, current can flow in to or out from the body node, setting its voltage. The constant is kept zero at all times, except when it is desired to change the body voltage. The body voltage can be reset at any time to solve the problem of successive delays in one simulation run and resetting the voltage before each delay measurement starts. To solve the problem of predicting the delay in a delay predictor (for example, NDR rules generation), the offset from the body voltage as a part of the best case/worst case determination is included.
摘要翻译： 用于编码为用于基于SOI的FET逻辑设计的设计软件的电子设计模型中的方法包括在模拟期间的任何时间，模拟SOI器件并将浮动体电压设置为任何所需值，通过向模型添加理想 电压源，其值是期望的体电压，与理想电流源串联，其值为恒定倍数的电压。 当常数为零时，电流不能流动，任何附加的组件对电路都没有影响。 当常数不为零时，所述理想电流源似乎与电阻器相同，使得电流可以流入或流出体节点，从而设定其电压。 恒定值始终保持为零，除非需要改变体电压。 可以随时重置体电压，以解决一次模拟运行中连续延迟的问题，并在每次延迟测量开始之前复位电压。 为了解决预测延迟预测器中的延迟（例如，NDR规则生成）的问题，包括作为最佳情况/最坏情况判定的一部分的与体电压的偏移。
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7.发明申请公开(公告)号：US20100001804A1
公开(公告)日：2010-01-07
申请号：US12168138
申请日：2008-07-06
IPC分类号： H03L5/00
CPC分类号： H03L7/0995
摘要： A system to improve a voltage-controlled oscillator may include a voltage-controlled oscillator. The system may also include a switch to control a first voltage passing through the voltage-controlled oscillator based upon a digital tune bit used to control the voltage-controlled oscillator's gain.
摘要翻译： 改进压控振荡器的系统可以包括压控振荡器。 该系统还可以包括用于基于用于控制压控振荡器的增益的数字调谐位来控制通过压控振荡器的第一电压的开关。
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公开(公告)号：US07084462B1
公开(公告)日：2006-08-01
申请号：US10907796
申请日：2005-04-15
IPC分类号： H01L31/0392
CPC分类号： H01L27/1203 , H01L27/088 , H01L29/7833 , H01L29/78615
摘要： A first or primary field effect transistor (“FET”) is separated from a body contact thereto by one or more second FETs that are placed electrically in parallel with the first FET. In this way, the body of the first FET can be extended into the region occupied by the second FET to allow contact to be made to the body of the first FET. In one embodiment, the gate conductor of the first FET and a gate conductor of the second FET are integral parts of a unitary conductive pattern. The unitary conductive pattern is made desirably small, and can be made as small as the smallest predetermined linewidth for gate conductors on an integrated circuit which includes the body-contacted FET. In this way, area and parasitic capacitance are kept small.
摘要翻译： 第一或一次场效应晶体管（“FET”）通过与第一FET并联放置的一个或多个第二FET与其体接触分离。 以这种方式，第一FET的主体可以扩展到由第二FET占据的区域，以允许与第一FET的主体接触。 在一个实施例中，第一FET的栅极导体和第二FET的栅极导体是整体导电图案的整体部分。 整体式导电图案理想地小，并且可以制成与包括身体接触的FET的集成电路上的栅极导体的最小预定线宽一样小。 以这种方式，面积和寄生电容保持较小。
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公开(公告)号：US06816824B2
公开(公告)日：2004-11-09
申请号：US09294178
申请日：1999-04-19
IPC分类号： G06F1750
CPC分类号： G06F17/5036
摘要： Low-conductance and high-conductance IV characteristics (models) are created using the low and high end of their body voltage ranges, respectively. The body voltage of the device (FET) is initialized to the low end of range at time zero, and then a transient, two dimensional sweep of gate and drain voltages is performed. Drain currents are measured in this two dimensional region and are used to create a piecewise, linear IV model of device. The process is repeated for the highest body voltage. This process differs significantly from prior art bulk device characterization techniques, which did not have to initialize body voltage or perform a transient analysis. The body voltage is modulating during the switching event due to the gate-to-body and diffusion-to-body coupling; and thus only a transient analysis can properly model these coupling effects.
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公开(公告)号：US4728814A
公开(公告)日：1988-03-01
申请号：US915467
申请日：1986-10-06
申请人： George E. Smith, III
发明人： George E. Smith, III
CPC分类号： H03K5/1534
摘要： An impulse generator for detecting an edge of an input pulse. The impulse generator comprises a first and second transistors connected to turn on at the occurrence of a signal pulse on an input line, with the second transistor connected to operate in its inverse mode so that it has a longer turn-on time. The second transistor is connected in such a manner as to draw current away from the base of the first transistor when the second transistor turns on, thereby causing an impulse to be generated at the output terminal of the first transistor, regardless of the width of the input pulse.
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