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公开(公告)号：US06177708B1
公开(公告)日：2001-01-23
申请号：US09324324
申请日：1999-06-02
IPC分类号： H01L2941
CPC分类号： H01L27/1203 , H01L29/42384 , H01L29/78606 , H01L29/78618
摘要： A self-aligned SOI FET device with an “L” shaped gate structure allows an integral diode junction to be formed between the source and the body of the device. Two devices with this gate geometry can be advantageously placed side-by-side in a single rx opening that could accommodate but a single device with a “T” shaped gate structure. The devices in accordance with the teachings of this invention can be easily formed using standard prior art SOI processing steps. An aspect of this invention includes the use of these novel SOI devices with their body and source connected together in circuit applications, such as memory cell sense amplifiers, where high speed operation commends the use of SOI technology, but physical space considerations have limited their application.
摘要翻译： 具有“L”形栅极结构的自对准SOI FET器件允许在器件的源极和主体之间形成整体二极管结。 具有该栅极几何形状的两个器件可以有利地并排布置在可容纳但具有“T”形栅极结构的单个器件的单个rx开口中。 根据本发明的教导的器件可以使用标准的现有技术的SOI处理步骤容易地形成。 本发明的一个方面包括使用这些新颖的SOI器件，其主体和源极在诸如存储器单元读出放大器的电路应用中连接在一起，其中高速操作表示使用SOI技术，但是物理空间考虑限制了它们的应用 。
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公开(公告)号：US20130077415A1
公开(公告)日：2013-03-28
申请号：US13247362
申请日：2011-09-28
IPC分类号： G11C7/00
CPC分类号： G11C7/00 , G11C7/02 , G11C7/04 , G11C11/417 , G11C11/419
摘要： An apparatus and method for combating the effects of bias temperature instability (BTI) in a memory cell. Bit lines connecting to a memory cell contain two alternate paths criss-crossing to connect a lower portion of a first bit line to an upper portion of a second bit line, and to connect a lower portion of the second bit line to an upper portion of the first bit line. Alternative to activating transistors on the bit lines to read and write to the memory cell, transistors on the alternative paths may be activated to read and write to the memory cell from the opposite bit lines. The memory cell may be read through the bit lines to a sense amplifier, the transistors on the bit lines are subsequently deactivated and the transistors on the alternate paths are activated to write transposed bit values to the memory cell, thereby reversing the biases.
摘要翻译： 一种用于抵抗存储单元中偏置温度不稳定性（BTI）的影响的装置和方法。 连接到存储器单元的位线包含两个交替的交替路径，以将第一位线的下部连接到第二位线的上部，并且将第二位线的下部连接到第二位线的上部 第一个位线。 在位线上激活晶体管以读取和写入存储器单元的替代方案是替代路径上的晶体管可被激活以从相对的位线读取和写入存储器单元。 存储器单元可以通过位线读取到读出放大器，位线上的晶体管随后被去激活，并且激活交替路径上的晶体管以将转置的位值写入存储器单元，从而反转偏置。
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3.发明授权Optimizing SRAM performance over extended voltage or process range using self-timed calibration of local clock generator 有权使用本地时钟发生器的自定时校准优化扩展电压或过程范围内的SRAM性能公开(公告)号：US07864625B2
公开(公告)日：2011-01-04
申请号：US12244286
申请日：2008-10-02
CPC分类号： G11C11/417 , G11C7/22 , G11C11/419
摘要： A delay circuit has a fixed delay path at a lower voltage level, a level converter, and an adjustable delay path at a higher voltage level. The fixed delay path includes an inverter chain, and the adjustable delay path includes serially-connected delay elements selectively connected to the circuit output. In an application for a local clock buffer of a static, random-access memory (SRAM), the lower voltage level is that of the local clock buffer, and the higher voltage level is that of the SRAM. These voltages may vary in response to dynamic voltage scaling, requiring re-calibration of the adjustable delay path. The adjustable delay path may be calibrated by progressively increasing the read access time of the SRAM array until a contemporaneous read operation returns the correct output, or by using a replica SRAM path to simulate variations in delay with changes in voltage supply.
摘要翻译： 延迟电路具有在较低电压电平的固定延迟路径，电平转换器和在较高电压电平下的可调延迟路径。 固定延迟路径包括反相器链，并且可调延迟路径包括选择性地连接到电路输出的串联连接的延迟元件。 在静态随机存取存储器（SRAM）的本地时钟缓冲器的应用中，较低的电压电平是本地时钟缓冲器的电平，而较高的电压电平是SRAM的电压电平。 这些电压可以响应于动态电压缩放而变化，需要重新校准可调延迟路径。 可调整的延迟路径可以通过逐渐增加SRAM阵列的读取访问时间来校准，直到同时读取操作返回正确的输出，或者通过使用复制SRAM路径来模拟延迟随电压变化的变化。
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公开(公告)号：US07847618B2
公开(公告)日：2010-12-07
申请号：US11970771
申请日：2008-01-08
申请人： Fadi H. Gebara , Jente B. Kuang , Abraham Mathews
发明人： Fadi H. Gebara , Jente B. Kuang , Abraham Mathews
IPC分类号： H03K3/01
CPC分类号： H02M3/073 , H02M2003/077 , H03L5/00
摘要： A distributed charge pump system uses a delay element and frequency dividers to generate out of phase pump clock signals that drive different charge pumps, to offset peak current clock edges for each charge pump and thereby reduce overall peak power. Clock signal division and phase offset may be extended to multiple levels for further smoothing of the pump clock signal transitions. A dual frequency divider may be used which receives the clock signal and its complement, and generates two divided signals that are 90° out of phase. In an illustrative embodiment the clock generator comprises a variable-frequency clock source, and a voltage regulator senses an output voltage of the charge pumps, generates a reference voltage based on a currently selected frequency of the variable-frequency clock source, and temporarily disables the charge pumps (by turning off local pump clocks) when the output voltage is greater than the reference voltage.
摘要翻译： 分布式电荷泵系统使用延迟元件和分频器产生驱动不同电荷泵的异相泵浦时钟信号，以抵消每个电荷泵的峰值电流时钟边缘，从而降低总体峰值功率。 时钟信号分频和相位偏移可以扩展到多个级别，以进一步平滑泵时钟信号转换。 可以使用双分频器，其接收时钟信号及其补码，并产生相位差为90°的两个分频信号。 在说明性实施例中，时钟发生器包括可变频率时钟源，并且电压调节器感测电荷泵的输出电压，基于当前选择的可变频率时钟源的频率产生参考电压，并暂时禁用 当输出电压大于参考电压时，电荷泵（通过关闭本地泵浦时钟）。
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公开(公告)号：US20100220541A1
公开(公告)日：2010-09-02
申请号：US12778960
申请日：2010-05-12
申请人： Fadi H. Gebara , Jente B. Kuang , Abraham Mathews
发明人： Fadi H. Gebara , Jente B. Kuang , Abraham Mathews
CPC分类号： H02M3/07 , G11C5/145 , G11C11/4074 , G11C2207/104
摘要： A switched-capacitor charge pump comprises a two-phase charging circuit, cross-coupled transistors connected to output nodes of the switched capacitors, and a pump output connected to source terminals of the cross-coupled transistors. The charge pump has side transistors for boosting charge transfer, and gating logic of the side transistors includes level shifters which control connections to the pump output or a reference voltage. Negative and positive charge pump embodiments are provided. The charging circuit advantageously utilizes non-overlapping wide and narrow clock signals to generate multiple gating signals. The pump clock circuit preferably provides independent, programmable adjustment of the widths of the wide and narrow clock signals. An override mode can be provided using clamping circuits which shunt the pump output to the second nodes of the switched capacitors.
摘要翻译： 开关电容器电荷泵包括两相充电电路，连接到开关电容器的输出节点的交叉耦合晶体管和连接到交叉耦合晶体管的源极端子的泵浦输出。 电荷泵具有用于升压电荷转移的侧晶体管，并且侧晶体管的选通逻辑包括电平转换器，其控制与泵输出的连接或参考电压。 提供负电荷泵和正电荷泵实施例。 充电电路有利地利用非重叠的宽和窄的时钟信号来产生多个门控信号。 泵时钟电路优选地提供宽和窄时钟信号的宽度的独立的可编程调整。 可以使用将泵浦输出分流到开关电容器的第二节点的钳位电路来提供覆盖模式。
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公开(公告)号：US07760010B2
公开(公告)日：2010-07-20
申请号：US11927784
申请日：2007-10-30
申请人： Fadi H. Gebara , Jente B. Kuang , Abraham Mathews
发明人： Fadi H. Gebara , Jente B. Kuang , Abraham Mathews
CPC分类号： H02M3/07 , G11C5/145 , G11C11/4074 , G11C2207/104
摘要： A switched-capacitor charge pump comprises a two-phase charging circuit, cross-coupled transistors connected to output nodes of the switched capacitors, and a pump output connected to source terminals of the cross-coupled transistors. The charge pump has side transistors for boosting charge transfer, and gating logic of the side transistors includes level shifters which control connections to the pump output or a reference voltage. Negative and positive charge pump embodiments are provided. The charging circuit advantageously utilizes non-overlapping wide and narrow clock signals to generate multiple gating signals. The pump clock circuit preferably provides independent, programmable adjustment of the widths of the wide and narrow clock signals. An override mode can be provided using clamping circuits which shunt the pump output to the second nodes of the switched capacitors.
摘要翻译： 开关电容器电荷泵包括两相充电电路，连接到开关电容器的输出节点的交叉耦合晶体管和连接到交叉耦合晶体管的源极端子的泵浦输出。 电荷泵具有用于升压电荷转移的侧晶体管，并且侧晶体管的选通逻辑包括电平转换器，其控制与泵输出的连接或参考电压。 提供负电荷泵和正电荷泵实施例。 充电电路有利地利用非重叠的宽和窄的时钟信号来产生多个门控信号。 泵时钟电路优选地提供宽和窄时钟信号的宽度的独立的可编程调整。 可以使用将泵浦输出分流到开关电容器的第二节点的钳位电路来提供覆盖模式。
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公开(公告)号：US07719315B2
公开(公告)日：2010-05-18
申请号：US11554666
申请日：2006-10-31
IPC分类号： H03K19/00
CPC分类号： G06F1/10 , G01R31/318552
摘要： A programmable clock generator circuit receives control signals and a global clock and generates a pulsed data clock and a scan clock in response to gating signals. The clock generator has data clock and scan clock feed-forward paths and a single feedback path. Delay control signals program delay elements in the feedback path and logic gates reshape and generate a feedback clock signal. The global clock and the feedback clock signal are combined to generates a pulsed local clock signal. A scan clock feed-forward circuit receives the local clock and generates the scan clock. A data clock feed-forward circuit receives the local clock and generates the data clock with a logic controlled delay relative to the local clock signal. The feedback clock is generated with controlled delay thereby modifying the pulse width of the data and scan clocks independent of the controlled delay of the data clock feed-forward path.
摘要翻译： 可编程时钟发生器电路接收控制信号和全局时钟，并响应门控信号产生脉冲数据时钟和扫描时钟。 时钟发生器具有数据时钟和扫描时钟前馈路径和单个反馈路径。 延迟控制信号在反馈路径中的程序延迟元件和逻辑门重新形成并产生反馈时钟信号。 全局时钟和反馈时钟信号被组合以产生脉冲本地时钟信号。 扫描时钟前馈电路接收本地时钟并产生扫描时钟。 数据时钟前馈电路接收本地时钟并产生相对于本地时钟信号的逻辑控制延迟的数据时钟。 以受控的延迟产生反馈时钟，从而修改数据的脉冲宽度和扫描时钟，而与数据时钟前馈路径的受控延迟无关。
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公开(公告)号：US20100102854A1
公开(公告)日：2010-04-29
申请号：US12621763
申请日：2009-11-19
IPC分类号： H03K5/22
CPC分类号： H03K5/1534
摘要： A circular edge detector on an integrated circuit including a plurality of edge detector cells, each of the plurality of edge detector cells having an input select block operable to receive a data signal and a previous cell signal and to generate a present cell signal, and a state capture block operably connected to receive the present cell signal. The present cell signal of each of the plurality of edge detector cells is provided to a next of the plurality of edge detector cells as the previous cell signal for the next of the plurality of edge detector cells, and the present cell signal from a last edge detector cell is provided to a first edge detector cell as the previous cell signal for the first edge detector cell.
摘要翻译： 在包括多个边缘检测器单元的集成电路上的圆形边缘检测器，所述多个边缘检测器单元中的每一个具有可操作以接收数据信号和先前信元信号并产生当前信元信号的输入选择块，以及 状态捕捉块可操作地连接以接收当前信元信号。 将多个边缘检测器单元中的每一个的当前单元信号提供给多个边缘检测器单元中的下一个，作为用于下一个边缘检测器单元的先前单元信号，并且来自最后边沿的当前单元信号 检测器单元被提供给第一边缘检测器单元作为用于第一边缘检测器单元的先前单元信号。
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9.发明申请Optimizing Sram Performance over Extended Voltage or Process Range Using Self-Timed Calibration of Local Clock Generator 有权使用本地时钟发生器的自定时校准优化扩展电压或过程范围的串行性能公开(公告)号：US20100085823A1
公开(公告)日：2010-04-08
申请号：US12244286
申请日：2008-10-02
CPC分类号： G11C11/417 , G11C7/22 , G11C11/419
摘要： A delay circuit has a fixed delay path at a lower voltage level, a level converter, and an adjustable delay path at a higher voltage level. The fixed delay path includes an inverter chain, and the adjustable delay path includes serially-connected delay elements selectively connected to the circuit output. In an application for a local clock buffer of a static, random-access memory (SRAM), the lower voltage level is that of the local clock buffer, and the higher voltage level is that of the SRAM. These voltages may vary in response to dynamic voltage scaling, requiring re-calibration of the adjustable delay path. The adjustable delay path may be calibrated by progressively increasing the read access time of the SRAM array until a contemporaneous read operation returns the correct output, or by using a replica SRAM path to simulate variations in delay with changes in voltage supply.
摘要翻译： 延迟电路具有在较低电压电平的固定延迟路径，电平转换器和在较高电压电平下的可调延迟路径。 固定延迟路径包括反相器链，并且可调延迟路径包括选择性地连接到电路输出的串联连接的延迟元件。 在静态随机存取存储器（SRAM）的本地时钟缓冲器的应用中，较低的电压电平是本地时钟缓冲器的电平，而较高的电压电平是SRAM的电压电平。 这些电压可以响应于动态电压缩放而变化，需要重新校准可调延迟路径。 可调整的延迟路径可以通过逐渐增加SRAM阵列的读取访问时间来校准，直到同时读取操作返回正确的输出，或者通过使用复制SRAM路径来模拟延迟随电压变化的变化。
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公开(公告)号：US07545690B2
公开(公告)日：2009-06-09
申请号：US11741187
申请日：2007-04-27
申请人： Jente B. Kuang , Jerry C. Kao , Hung Cai Ngo , Kevin J. Nowka
发明人： Jente B. Kuang , Jerry C. Kao , Hung Cai Ngo , Kevin J. Nowka
CPC分类号： G11C29/50 , G11C11/41 , G11C29/50012 , G11C2029/1204
摘要： A method for evaluating memory cell performance provides for circuit delay and performance measurements in an actual memory circuit environment. A row in a memory array is enabled along with a set of drive devices that couple each bitline pair to the next in complement fashion to form a cascade of memory cells. The drive devices can be inverters and the inverters can be sized to simulate the bitline read pre-charge device and the write state-forcing device so that the cascade operates under the same loading/drive conditions as the operational with memory cell read/write circuits. The last and first bitline in the row can be cascaded, providing a ring oscillator or the delay of the cascade can be measured in response to a transition introduced at the head of the cascade. Weak read and/or weak write conditions can be measured by selective loading.
摘要翻译： 用于评估存储器单元性能的方法在实际存储器电路环境中提供电路延迟和性能测量。 存储器阵列中的行与一组驱动装置一起被启用，这些驱动装置将每个位线对以互补方式耦合到下一个位置以形成级联的存储器单元。 驱动装置可以是逆变器，并且逆变器的大小可以模拟位线读取预充电装置和写入状态强制装置，使得级联在与存储单元读/写电路的操作相同的加载/驱动条件下操作 。 该行中的最后一个和第一个位线可以级联，提供环形振荡器，或者响应于在级联头部引入的转换，可以测量级联的延迟。 弱写入条件和/或弱写入条件可以通过选择性加载来测量。
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