SOI FET body contact structure
    1.
    发明授权
    SOI FET body contact structure 有权
    SOI FET体接触结构

    公开(公告)号:US06177708B1

    公开(公告)日:2001-01-23

    申请号:US09324324

    申请日:1999-06-02

    IPC分类号: H01L2941

    摘要: A self-aligned SOI FET device with an “L” shaped gate structure allows an integral diode junction to be formed between the source and the body of the device. Two devices with this gate geometry can be advantageously placed side-by-side in a single rx opening that could accommodate but a single device with a “T” shaped gate structure. The devices in accordance with the teachings of this invention can be easily formed using standard prior art SOI processing steps. An aspect of this invention includes the use of these novel SOI devices with their body and source connected together in circuit applications, such as memory cell sense amplifiers, where high speed operation commends the use of SOI technology, but physical space considerations have limited their application.

    摘要翻译: 具有“L”形栅极结构的自对准SOI FET器件允许在器件的源极和主体之间形成整体二极管结。 具有该栅极几何形状的两个器件可以有利地并排布置在可容纳但具有“T”形栅极结构的单个器件的单个rx开口中。 根据本发明的教导的器件可以使用标准的现有技术的SOI处理步骤容易地形成。 本发明的一个方面包括使用这些新颖的SOI器件,其主体和源极在诸如存储器单元读出放大器的电路应用中连接在一起,其中高速操作表示使用SOI技术,但是物理空间考虑限制了它们的应用 。

    SOI sense amplifier with body contact structure
    2.
    发明授权
    SOI sense amplifier with body contact structure 失效
    SOI感应放大器具有机身接触结构

    公开(公告)号:US6154091A

    公开(公告)日:2000-11-28

    申请号:US324498

    申请日:1999-06-02

    摘要: A self-aligned SOI FET device with an "L" shaped gate structure allows an integral diode junction to be formed between the source and the body of the device. Two devices with this gate geometry can be advantageously placed side-by-side in a single rx opening that could accommodate but a single device with a "T" shaped gate structure. The devices in accordance with the teachings of this invention can be easily formed using standard prior art SOI processing steps. An aspect of this invention includes the use of these novel SOI devices with their body and source connected together in circuit applications, such as memory cell sense amplifiers, where high speed operation commends the use of SOI technology, but physical space considerations have limited their application.

    摘要翻译: 具有“L”形栅极结构的自对准SOI FET器件允许在器件的源极和主体之间形成整体二极管结。 具有该栅极几何形状的两个器件可以有利地并排布置在可容纳但具有“T”形栅极结构的单个器件的单个rx开口中。 根据本发明的教导的器件可以使用标准的现有技术的SOI处理步骤容易地形成。 本发明的一个方面包括使用这些新颖的SOI器件,其主体和源极在诸如存储器单元读出放大器的电路应用中连接在一起,其中高速操作表示使用SOI技术,但是物理空间考虑限制了它们的应用 。

    Method for Achieving An Efficient Statistical Optimization of Integrated Circuits
    3.
    发明申请
    Method for Achieving An Efficient Statistical Optimization of Integrated Circuits 有权
    实现集成电路高效统计优化的方法

    公开(公告)号:US20140040844A1

    公开(公告)日:2014-02-06

    申请号:US13564751

    申请日:2012-08-02

    IPC分类号: G06F17/50

    CPC分类号: G06F17/5031

    摘要: Method for performing timing closure of integrated circuits in the presence of manufacturing and environmental variations. The starting design is analyzed using statistical static timing analysis to determine timing violations. Each timing violation in its statistical canonical form is examined. In a first aspect of the invention, the canonical failing slack is inspected to determine what type of move is most likely to fix the timing violation taking into account all relevant manufacturing and environmental variations. In a second aspect of the invention, pre-characterized moves such as insertion of delay pad cells are evaluated for their ability to fix the timing violation without triggering timing, and the best move or set of moves is selected.

    摘要翻译: 在存在制造和环境变化的情况下执行集成电路的定时关闭的方法。 使用统计静态时序分析来分析起始设计,以确定时序违规。 检查其统计规范形式的每个时间违规。 在本发明的第一方面,检查规范的故障松弛以确定哪种类型的移动最有可能在考虑到所有相关的制造和环境变化的情况下修复定时违规。 在本发明的第二方面中,评估了诸如插入延迟垫单元之类的预先表征的移动能够固定定时违反而不触发定时,并且选择最佳移动或移动集合。

    Combination oil scrapper ring/gas seal assembly
    4.
    发明授权
    Combination oil scrapper ring/gas seal assembly 有权
    组合刮油环/气密封组件

    公开(公告)号:US06959930B2

    公开(公告)日:2005-11-01

    申请号:US10438474

    申请日:2003-05-15

    IPC分类号: F16J15/26 F16J9/12

    CPC分类号: F16J15/26

    摘要: A ring assembly, including a first oil scraper ring, a center oil scraper ring and a gas seal ring, adapted for disposition in a single groove of a packing cup which can be stationarily mounted over and around a reciprocally movable piston rod of a gas compressor. The function of the assembly is to both scrape lubricating oil from the piston rod for return to one side of the cup and to provide a seal against gas leakage from an opposite side of the cup, both along the piston rod under the seal ring and between the seal ring and opposing sides of the center ring and groove to prevent mixing of gas with the oil and escape of gas from the compressor. The center ring features a tapered outer peripheral surface portion. An annular side loading element, which can be a garter spring, is mounted in compression around the center ring so as to bear against the tapered surface portion and against an adjacent side of the first ring. The element thus side loads the first ring, by urging it against one side of the groove and oppositely side loads the center ring and seal ring to force one against the other and to urge the seal ring tightly against an opposite side wall of the groove to effect a satisfactory gas seal. The first ring and center ring, together, provide three separate and axially spaced apart oil scraper edges.

    摘要翻译: 一种环组件,包括第一刮油环,中心刮油环和气密封环,其适于配置在填料杯的单个槽中,其可以固定地安装在气体压缩机的往复运动的活塞杆上 。 该组件的功能是既要从活塞杆上刮去润滑油,以便返回到杯的一侧,并且提供密封件,以防止来自杯的相对侧的气体泄漏,两者沿密封圈下方的活塞杆和第二 密封环和中心环和槽的相对侧,以防止气体与油的混合和气体从压缩机逸出。 中心环具有锥形外周面部分。 环形侧装载元件可以是一个拉杆弹簧,围绕中心环压缩安装,以抵靠锥形表面部分并抵靠第一环的相邻侧。 因此,元件通过将其推向槽的一侧来加载第一环,并且相反侧装载中心环和密封环以迫使一个抵靠另一个并且将密封环紧紧地推靠在槽的相对侧壁上 实现令人满意的气密封。 第一环和中心环一起提供三个独立且轴向隔开的刮油边。

    Dual channel d.c. low noise measurement system and test methodology
    5.
    发明授权
    Dual channel d.c. low noise measurement system and test methodology 失效
    双通道直流 低噪声测量系统和测试方法

    公开(公告)号:US5563517A

    公开(公告)日:1996-10-08

    申请号:US442556

    申请日:1995-05-16

    IPC分类号: G01R31/26 G01R29/26 H01L21/66

    CPC分类号: G01R29/26

    摘要: A test system having an improved physical layout and electrical design allows the 1/f noise of metal interconnects to be measured at levels close to that of Johnson or thermal noise. A detailed description of examples of operation of the test system provides evidence of the effectiveness of the test system in minimizing system noise to a level significantly lower than Johnson noise. This permits quantitative measurment of the noise contribution attributable to variations in cross-sectional area of connections for various applications and for qualitative prediction of electromigration lifetimes of metal films, particularly aluminum, having different microstructures. The test system includes an enclosure which includes several nested groups of housings including a sample oven within a device under test box which is, in turn, contained within the system enclosure. Wire wound resistors powered by a DC power supply are used to provide heating without interfering with measurement of 1/f noise of a device under test (D.U.T.). A biasing circuit and a bank of batteries are also provided with separate enclosures within the system enclosure.

    摘要翻译: 具有改进的物理布局和电气设计的测试系统允许以接近Johnson或热噪声的水平测量金属互连的1 / f噪声。 测试系统操作示例的详细描述提供了测试系统在将系统噪声降至明显低于约翰逊噪声水平的有效性的证据。 这允许由于各种应用的连接的横截面积的变化以及用于定性预测具有不同微结构的金属膜,特别是铝的电迁移寿命的噪声贡献的定量测量。 该测试系统包括一个外壳,该外壳包括若干嵌套的外壳组,其中包括在被测箱的设备内的样品烘箱,该烘箱也被包含在系统外壳内。 由直流电源供电的绕线电阻器用于提供加热,而不会干扰被测器件(D.U.T.)的1 / f噪声的测量。 偏置电路和电池组还在系统外壳内设置有单独的外壳。

    Process for managing complex pre-wired net segments in a VLSI design
    6.
    发明授权
    Process for managing complex pre-wired net segments in a VLSI design 有权
    在VLSI设计中管理复杂的预先有线网段的过程

    公开(公告)号:US07681169B2

    公开(公告)日:2010-03-16

    申请号:US11846577

    申请日:2007-08-29

    IPC分类号: G06F17/50

    CPC分类号: G06F17/5077

    摘要: A method for pre-wiring through multiple levels of metal using flues includes steps of: receiving information comprising flue geometries and flue properties; producing multiple routing patterns of a design for the flues; identifying macro instance terminals to be pre-wired in the design; selecting at least one of the routing patterns for the macro instance terminals in the design to avoid blockage; and instantiating the design such that the flues can be manipulated as vias.

    摘要翻译: 使用烟道预先接线多层金属的方法包括以下步骤:接收包括烟道几何形状和烟道特性的信息; 生成针对流感的设计的多个路由模式; 识别要在设计中预先布线的宏实例终端; 在设计中选择用于宏实例终端的路由模式中的至少一个以避免阻塞; 并实例化设计,使得烟道可以被操纵为过孔。

    Dual channel D.C. low noise measurement system and test methodology
    8.
    发明授权
    Dual channel D.C. low noise measurement system and test methodology 失效
    双通道D.C.低噪声测量系统和测试方法

    公开(公告)号:US5434385A

    公开(公告)日:1995-07-18

    申请号:US970370

    申请日:1992-11-02

    CPC分类号: G01R29/26

    摘要: A test system having an improved physical layout and electrical design allows the 1/f noise of metal interconnects to be measured at levels close to that of Johnson or thermal noise. A detailed description of examples of operation of the test system provides evidence of the effectiveness of the test system in minimizing system noise to a level significantly lower than Johnson noise. This permits quantitative measurment of the noise contribution attributable to variations in cross-sectional area of connections for various applications and for qualitative prediction of electromigration lifetimes of metal films, particularly aluminum, having different microstructures. The test system includes an enclosure which includes several nested groups of housings including a sample oven within a device under test box which is, in turn, contained within the system enclosure. Wire wound resistors powered by a DC power supply are used to provide heating without interfering with measurement of 1/f noise of a device under test (D.U.T.). A biasing circuit and a bank of batteries are also provided with separate enclosures within the system enclosure.

    摘要翻译: 具有改进的物理布局和电气设计的测试系统允许以接近Johnson或热噪声的水平测量金属互连的1 / f噪声。 测试系统操作示例的详细描述提供了测试系统在将系统噪声降至明显低于约翰逊噪声水平的有效性的证据。 这允许由于各种应用的连接的横截面积的变化以及用于定性预测具有不同微结构的金属膜,特别是铝的电迁移寿命的噪声贡献的定量测量。 该测试系统包括一个外壳,该外壳包括若干嵌套的外壳组,其中包括在被测箱的设备内的样品烘箱,该烘箱也被包含在系统外壳内。 由直流电源供电的绕线电阻器用于提供加热,而不会干扰被测器件(D.U.T.)的1 / f噪声的测量。 偏置电路和电池组还在系统外壳内设置有单独的外壳。

    Compilable address magnitude comparator for memory array self-testing
    9.
    发明授权
    Compilable address magnitude comparator for memory array self-testing 有权
    可编程地址幅度比较器用于存储器阵列自检

    公开(公告)号:US06658610B1

    公开(公告)日:2003-12-02

    申请号:US09669117

    申请日:2000-09-25

    IPC分类号: G11C2900

    摘要: The present invention provides a method and apparatus that improves Built-In-Self-Test (BIST) flexibility without requiring the complexity of a compilable BIST circuit. Additionally, the present invention provides the ability to use a single BIST to test multiple memory arrays of different sizes. The preferred embodiment of the present invention provides a compilable address magnitude comparator to facilitate BIST testing of different size memory arrays without requiring customization of the BIST controller. The preferred embodiment compilable address magnitude comparator is compiled within the compilable memory arrays of the ASIC to allow a single BIST controller to test multiple sizes of memory arrays without requiring that the BIST controller itself be compilable. In the preferred embodiment, the compilable magnitude address comparator overrides the self-test signal from the BIST when the BIST attempts to test addresses that do not exist in the memory. As such, the BIST is prevented from writing to addresses that do not exist, and does not receive error signals from those addresses. Thus, the BIST controller is able to test memory arrays without regard for their particular size. Furthermore, a single BIST controller can then be used to test multiple memory arrays of different sizes in the ASIC, again reducing device complexity.

    摘要翻译: 本发明提供了一种改进内置自测(BIST)灵活性的方法和装置,而不需要可编译BIST电路的复杂性。 此外,本发明提供了使用单个BIST来测试不同大小的多个存储器阵列的能力。 本发明的优选实施例提供可编译的地址幅度比较器,以便于不需要定制BIST控制器的不同大小的存储器阵列的BIST测试。 优选实施例可编译地址幅度比较器被编译在ASIC的可编译存储器阵列内,以允许单个BIST控制器测试存储器阵列的多个大小,而不需要BIST控制器本身可编译。 在优选实施例中,当BIST尝试测试存储器中不存在的地址时,可编译幅度地址比较器覆盖来自BIST的自检信号。 因此,BIST被阻止写入不存在的地址,并且不从这些地址接收到错误信号。 因此,BIST控制器能够测试存储器阵列,而不考虑其特定大小。 此外,可以使用单个BIST控制器来测试ASIC中不同大小的多个存储器阵列,从而降低器件的复杂性。

    Clinical event outcome scoring system employing a severity of illness clinical key and method

    公开(公告)号:US11848106B1

    公开(公告)日:2023-12-19

    申请号:US17215761

    申请日:2021-03-29

    申请人: Michael H. Wood

    发明人: Michael H. Wood

    IPC分类号: G16H50/20 G16H50/30 G16H40/20

    CPC分类号: G16H50/30 G16H40/20 G16H50/20

    摘要: A clinical event outcome scoring system and method are used to determine a Severity of Illness Clinical Key (SICK) score, which is a probable degree of successful outcome for a patient about to undergo a specific clinical event, such as for example, coronary bypass surgery, hip replacement, bariatric surgery, discharge from a hospital for home recovery, a course of chemotherapy, radiation, or other treatment protocol. The system and method analyzes historical patient data to generate a statistical model for each specific clinical event of interest, which can then be used to determine a SICK score for a patient about to undergo the same clinical event. In some embodiments, the statistical model can be “fine-tuned” to render subcategories of statistical models tailored for certain patient populations about to undergo the same clinical event. In some embodiments, the statistical model can be augmented to take into account “outliers,” who have extra challenges not taken into account with the primary statistical model.