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公开(公告)号：US08086892B2
公开(公告)日：2011-12-27
申请号：US12886457
申请日：2010-09-20
CPC分类号： G06F1/08
摘要： A microcode configurable frequency clock that may be used to control the speed of high speed comparison in an operational optical transceiver. The frequency clock includes a memory and a logic circuit. The memory receives microcode generated data relating to the desired speed of comparison. The logic circuit is configured to receive an input clock signal and to produce an output clock signal by frequency dividing the input signal based on the microcode generated data. The output clock is used to control the speed of comparison in the optical transceiver.
摘要翻译： 可用于控制在操作光收发器中的高速比较速度的微码可配置频率时钟。 频率时钟包括存储器和逻辑电路。 存储器接收与所需的比较速度有关的微码生成数据。 逻辑电路被配置为接收输入时钟信号并且通过基于微码产生的数据对输入信号进行分频来产生输出时钟信号。 输出时钟用于控制光收发器中的比较速度。
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公开(公告)号：US07653314B2
公开(公告)日：2010-01-26
申请号：US11468246
申请日：2006-08-29
CPC分类号： H04B10/40
摘要： An optical transceiver that custom logs information based on input from a host computing system (hereinafter referred to as a “host”). The optical transceiver receives input from the host concerning which operational information to log; the operational information may include statistical data about system operation, or measured parameters, or any other measurable system characteristic. The input from the host may also specify one or more storage locations corresponding to the identified operational information. If one or more storage locations are specified, the optical transceiver logs the information to the corresponding storage locations, which may be an on-transceiver persistent memory, the memory of the host or any other accessible logging location. Additionally, the input from the host may specify one or more actions to be performed when the identified information is logged. If one or more actions are specified, the optical transceiver performs the specified actions when the information is logged.
摘要翻译： 基于来自主机计算系统（以下称为“主机”）的输入来定制记录信息的光收发器。 光收发器从主机接收关于要登录的操作信息的输入; 操作信息可以包括关于系统操作或测量参数或任何其它可测量的系统特性的统计数据。 来自主机的输入还可以指定与所识别的操作信息相对应的一个或多个存储位置。 如果指定了一个或多个存储位置，光收发器将信息记录到对应的存储位置，存储位置可以是收发器上的持久存储器，主机的存储器或任何其他可访问的记录位置。 此外，来自主机的输入可以指定当记录所识别的信息时要执行的一个或多个动作。 如果指定了一个或多个动作，当收发信息被记录时，光收发器执行指定的动作。
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公开(公告)号：US07437078B2
公开(公告)日：2008-10-14
申请号：US10970529
申请日：2004-10-21
IPC分类号： H04B10/00
摘要： A telecommunications system and constituent integrated circuit that includes a post-amplifier assembly configured for communication with an optical receiver, a laser driver assembly configured for communication with the optical transmitter, and a controller assembly configured to control the post-amplifier and laser driver. The post-amplifier, the laser driver, and the controller assemblies are embodied on a single integrated circuit, thereby reducing manufacturing costs. Noise due to clock generation may be reduced by having the clock act on a transient basis, turning on when needed during the boot process, and turning off when not needed during normal operation.
摘要翻译： 一种电信系统和构成集成电路，其包括被配置为与光接收器通信的后置放大器组件，被配置为与光发射器通信的激光驱动器组件以及被配置为控制后置放大器和激光驱动器的控制器组件。 后置放大器，激光驱动器和控制器组件体现在单个集成电路上，从而降低制造成本。 通过使时钟作用在瞬时状态下，由于时钟产生引起的噪声可能会降低，在引导过程中需要时打开，并且在正常操作期间不需要时关闭。
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公开(公告)号：US07426586B2
公开(公告)日：2008-09-16
申请号：US10970530
申请日：2004-10-21
CPC分类号： G06F13/4072
摘要： Configuring chip I/O terminals such that they may be input, output, or bi-directional terminals. Furthermore, the I/O terminals may be configured with different signal sources if they are output or bi-directional terminals. In addition, the terminals may be configured to be inverted when operating in either direction. A mechanism is provided to change this configuration as needed, for example, to correspond to different pins on the package as appropriate given the package configuration and other implementation needs. This configurability allows for tremendous flexibility and independent between the chip on which the integrated circuit is embedded and the package.
摘要翻译： 配置芯片I / O端子，使其可以是输入，输出或双向端子。 此外，I / O端子可以被配置为具有不同的信号源，如果它们是输出或双向端子。 此外，端子可以被配置为在沿任一方向工作时被倒置。 提供了根据需要改变该配置的机制，例如，根据包装配置和其他实现需要，适当地对应于包上的不同引脚。 这种可配置性允许嵌入集成电路的芯片与封装之间的巨大的灵活性和独立性。
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公开(公告)号：US20080126619A1
公开(公告)日：2008-05-29
申请号：US11624582
申请日：2007-01-18
申请人： Gerald L. Dybsetter
发明人： Gerald L. Dybsetter
IPC分类号： G06F3/00
CPC分类号： G06F13/387
摘要： Mechanisms for configuring an integrated circuit to select one of multiple external device interfaces at a time to use during communication with external devices. The integrated circuit includes a control mechanism, a selection mechanism, and a plurality of external device interfaces. The plurality of device interfaces allow the integrated circuit to communicate with various external devices that support different communication protocols. The control mechanism is configured to designate the selection of one of the plurality of device interfaces for use in communicating with an external device. The control mechanism makes use of the selection mechanism to select the designated device interface to communicate with using the communication protocol supported by the selected interface. The communication may be receiving data from the interface or providing data to the interface. Non-selected interfaces are put in an inactive state.
摘要翻译： 用于配置集成电路以在与外部设备通信期间一次选择多个外部设备接口之一的机制。 集成电路包括控制机构，选择机构和多个外部设备接口。 多个设备接口允许集成电路与支持不同通信协议的各种外部设备进行通信。 控制机构被配置为指定用于与外部设备进行通信的多个设备接口之一的选择。 控制机制利用选择机制选择指定的设备接口，使用所选接口支持的通信协议进行通信。 通信可能正在从接口接收数据或向接口提供数据。 未选择的接口将处于非活动状态。
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公开(公告)号：US07346278B2
公开(公告)日：2008-03-18
申请号：US10817783
申请日：2004-04-02
IPC分类号： H04B10/08
CPC分类号： H04B10/07 , H04B10/0799 , H04B10/43 , H04B2210/08
摘要： Circuitry for monitoring the operation of an optoelectronic transceiver includes a sequence of interconnected signal processing circuits for processing an analog input signal and producing a digital result signal, where the analog signal represents one or more operating conditions of the optoelectronic transceiver. The sequence of signal processing circuits include gain circuitry for amplifying or attenuating the analog input signal by a gain value to produce a scaled analog signal, an analog to digital converter for converting the scaled analog signal into a first digital signal, and digital adjustment circuitry for digitally adjusting the first digital signal to produce the digital result signal. The digital adjustment circuitry includes shifting circuitry configured to shift an input digital signal in accordance with a shift value so as to produce a digital shifted signal. The digital result signal is stored in memory in predefined locations accessible by a host.
摘要翻译： 用于监测光电收发器的操作的电路包括一系列互连的信号处理电路，用于处理模拟输入信号并产生数字结果信号，其中模拟信号表示光电收发器的一个或多个操作条件。 信号处理电路的序列包括用于通过增益值放大或衰减模拟输入信号以产生缩放的模拟信号的增益电路，用于将缩放的模拟信号转换为第一数字信号的模数转换器，以及用于 数字调整第一数字信号以产生数字结果信号。 数字调节电路包括移位电路，其被配置为根据移位值移位输入数字信号，以产生数字移位信号。 数字结果信号存储在主机可访问的预定位置的存储器中。
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公开(公告)号：US06999011B2
公开(公告)日：2006-02-14
申请号：US10814440
申请日：2004-03-31
申请人： Daniel Case , Gerald L. Dybsetter , Jayne C. Hahin
发明人： Daniel Case , Gerald L. Dybsetter , Jayne C. Hahin
IPC分类号： H03M1/06
CPC分类号： H03M1/183
摘要： Microcode driven adjustment of analog scaling of an analog signal prior to being provided to an analog-to-digital converter. The microcode also causes the system to read the resulting digital value, and determine whether the scaling value should be adjusted for that analog signal. Accordingly, the microcode may cause the analog signal to be dynamically adjusted to be within the input range of the analog-to-digital converter, thereby allowing for more accurate digital conversions with lower resolution analog-to-digital converters. The microcode rapidly adjusts for any fluctuations in the input voltage. Accordingly, the analog signal may fluctuate, or even be multiplexed from a wide variety of different analog signal sources.
摘要翻译： 在将模拟信号提供给模数转换器之前，模拟量程缩放的微码驱动调整。 微码还使系统读取所得到的数字值，并确定是否应该为该模拟信号调整缩放值。 因此，微码可以使得模拟信号被动态地调整到模数转换器的输入范围内，从而允许用较低分辨率的模 - 数转换器进行更精确的数字转换。 微码可快速调整输入电压的任何波动。 因此，模拟信号可能波动，甚至可以从各种不同的模拟信号源复用。
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公开(公告)号：US08930434B2
公开(公告)日：2015-01-06
申请号：US11531074
申请日：2006-09-12
申请人： Gerald L. Dybsetter
发明人： Gerald L. Dybsetter
CPC分类号： G06F7/57 , G06F9/3001
摘要： The principles of the present invention relate to a multiply and divide circuit configured to interactively multiply and/or divide. The circuit may handle signed and unsigned values. The circuit comprises an instruction register configured to store a multiply or divide instruction, at one input register configured to store the multiply or divide operands, an Arithmetic Logic Unit (“ALU”) configured to add provided values, and configuration circuitry. The configuration circuitry responds to the instructions and performs the multiply or divide operation by iteratively providing values to the ALU.
摘要翻译： 本发明的原理涉及被配置为交互地乘法和/或除法的乘法和除法电路。 该电路可以处理带符号和无符号值。 电路包括指令寄存器，其被配置为在配置为存储乘法或除法运算的一个输入寄存器处存储乘法或除法指令，被配置为添加提供的值的算术逻辑单元（“ALU”）和配置电路。 配置电路响应指令，并通过迭代地向ALU提供值来执行乘法或除法运算。
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9.发明申请公开(公告)号：US20130148978A1
公开(公告)日：2013-06-13
申请号：US13426506
申请日：2012-03-21
申请人： Jason Y. Miao , Curtis B. Robinson, JR. , Georgios Kalogerakis , Gerald L. Dybsetter , Luke M. Ekkizogloy
发明人： Jason Y. Miao , Curtis B. Robinson, JR. , Georgios Kalogerakis , Gerald L. Dybsetter , Luke M. Ekkizogloy
CPC分类号： H04B10/50 , G02B6/4249 , G02B6/4292
摘要： Chip identification pads for identification of integrated circuits in an assembly. In one example embodiment, an integrated circuit (IC) assembly includes a controller, a plurality of ICs, a shared communication bus connecting the controller to the plurality of ICs and configured to enable communication between the controller and each of the plurality of ICs, and a set of one or more chip identification pads formed on each IC. Each set of chip identification pads has an electrical connection pattern. The electrical connection pattern of each set is distinct from the electrical connection pattern on every other set. Each distinct electrical connection pattern represents a unique identifier of the corresponding IC thereby enabling the controller to distinguish between the ICs.
摘要翻译： 用于识别组件中的集成电路的芯片识别板。 在一个示例性实施例中，集成电路（IC）组件包括控制器，多个IC，共享通信总线，其将控制器连接到多个IC并且被配置为实现控制器与多个IC中的每一个之间的通信，以及 在每个IC上形成的一组或多个芯片识别焊盘。 每组芯片识别板具有电连接图案。 每组的电连接模式与每隔一组的电连接模式不同。 每个不同的电连接模式表示相应IC的唯一标识符，从而使得控制器能够区分IC。
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公开(公告)号：US08229301B2
公开(公告)日：2012-07-24
申请号：US11220765
申请日：2005-09-07
摘要： An optical transceiver (or optical transmitter or optical receiver) that includes a memory and a processor, which receives and executes custom microcode from a host computing system (hereinafter referred to simply as a “host”). A user identifies desired optical transceiver operational features, each of which may be implemented using specific microcode. The memory receives custom microcode that aggregates all the specific microcode of the identified operational features from the host. The processor may later execute the custom microcode and cause the transceiver to perform the operational features.
摘要翻译： 包括存储器和处理器的光收发器（或光发射机或光接收机），其从主计算系统（以下简称为“主机”）接收并执行定制微代码。 用户识别所需的光收发器操作特征，每个操作特征可以使用特定的微码来实现。 存储器接收定制微码，其聚合来自主机的所识别的操作特征的所有特定微码。 处理器可以稍后执行定制微代码并使收发器执行操作特征。
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