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1.发明申请公开(公告)号：US20130148978A1
公开(公告)日：2013-06-13
申请号：US13426506
申请日：2012-03-21
申请人： Jason Y. Miao , Curtis B. Robinson, JR. , Georgios Kalogerakis , Gerald L. Dybsetter , Luke M. Ekkizogloy
发明人： Jason Y. Miao , Curtis B. Robinson, JR. , Georgios Kalogerakis , Gerald L. Dybsetter , Luke M. Ekkizogloy
CPC分类号： H04B10/50 , G02B6/4249 , G02B6/4292
摘要： Chip identification pads for identification of integrated circuits in an assembly. In one example embodiment, an integrated circuit (IC) assembly includes a controller, a plurality of ICs, a shared communication bus connecting the controller to the plurality of ICs and configured to enable communication between the controller and each of the plurality of ICs, and a set of one or more chip identification pads formed on each IC. Each set of chip identification pads has an electrical connection pattern. The electrical connection pattern of each set is distinct from the electrical connection pattern on every other set. Each distinct electrical connection pattern represents a unique identifier of the corresponding IC thereby enabling the controller to distinguish between the ICs.
摘要翻译： 用于识别组件中的集成电路的芯片识别板。 在一个示例性实施例中，集成电路（IC）组件包括控制器，多个IC，共享通信总线，其将控制器连接到多个IC并且被配置为实现控制器与多个IC中的每一个之间的通信，以及 在每个IC上形成的一组或多个芯片识别焊盘。 每组芯片识别板具有电连接图案。 每组的电连接模式与每隔一组的电连接模式不同。 每个不同的电连接模式表示相应IC的唯一标识符，从而使得控制器能够区分IC。
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2.发明授权Chip identification pads for identification of integrated circuits in an assembly 有权用于识别组件中的集成电路的芯片识别板公开(公告)号：US08882366B2
公开(公告)日：2014-11-11
申请号：US13426506
申请日：2012-03-21
申请人： Jason Y. Miao , Curtis B. Robinson, Jr. , Georgios Kalogerakis , Gerald L. Dybsetter , Luke M. Ekkizogloy
发明人： Jason Y. Miao , Curtis B. Robinson, Jr. , Georgios Kalogerakis , Gerald L. Dybsetter , Luke M. Ekkizogloy
IPC分类号： G02B6/36
CPC分类号： H04B10/50 , G02B6/4249 , G02B6/4292
摘要： Chip identification pads for identification of integrated circuits in an assembly. In one example embodiment, an integrated circuit (IC) assembly includes a controller, a plurality of ICs, a shared communication bus connecting the controller to the plurality of ICs and configured to enable communication between the controller and each of the plurality of ICs, and a set of one or more chip identification pads formed on each IC. Each set of chip identification pads has an electrical connection pattern. The electrical connection pattern of each set is distinct from the electrical connection pattern on every other set. Each distinct electrical connection pattern represents a unique identifier of the corresponding IC thereby enabling the controller to distinguish between the ICs.
摘要翻译： 用于识别组件中的集成电路的芯片识别板。 在一个示例性实施例中，集成电路（IC）组件包括控制器，多个IC，共享通信总线，其将控制器连接到多个IC并且被配置为实现控制器与多个IC中的每一个之间的通信，以及 在每个IC上形成的一组或多个芯片识别焊盘。 每组芯片识别板具有电连接图案。 每组的电连接模式与每隔一组的电连接模式不同。 每个不同的电连接模式表示相应IC的唯一标识符，从而使得控制器能够区分IC。
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公开(公告)号：US08819423B2
公开(公告)日：2014-08-26
申请号：US12323731
申请日：2008-11-26
摘要： An optical receiver comprising at least one processor and a memory including at least one of an encryption key or a decryption key and at least one of encryption microcode or decryption microcode that includes processor-executable instructions that, when executed by the at least one processor, cause the optical transceiver to perform the following: an act of performing an encryption or decryption operation on data received from a host computing system to thereby authenticate the optical transceiver.
摘要翻译： 一种光接收机，包括至少一个处理器和存储器，其包括加密密钥或解密密钥中的至少一个以及包括处理器可执行指令的加密微代码或解密微码码中的至少一个，当由至少一个处理器执行时， 使得光收发器执行以下操作：对从主计算系统接收的数据执行加密或解密操作从而认证光收发器的动作。
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公开(公告)号：US20090138709A1
公开(公告)日：2009-05-28
申请号：US12323731
申请日：2008-11-26
摘要： An optical receiver comprising at least one processor and a memory including at least one of an encryption key or a decryption key and at least one of encryption microcode or decryption microcode that includes processor-executable instructions that, when executed by the at least one processor, cause the optical transceiver to perform the following: an act of performing an encryption or decryption operation on data received from a host computing system to thereby authenticate the optical transceiver.
摘要翻译： 一种光接收机，包括至少一个处理器和存储器，其包括加密密钥或解密密钥中的至少一个以及包括处理器可执行指令的加密微代码或解密微码码中的至少一个，当由至少一个处理器执行时， 使得光收发器执行以下操作：对从主计算系统接收的数据执行加密或解密操作从而认证光收发器的动作。
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公开(公告)号：US08686765B2
公开(公告)日：2014-04-01
申请号：US13544327
申请日：2012-07-09
CPC分类号： H03K19/017509 , H03K19/017527
摘要： A circuit may include an input node configured to receive a signal and an output node configured to be coupled to a load. The circuit may also include a first circuit coupled between the input node and the output node. The first circuit may be configured to receive the signal and to drive the signal on the output node at a first voltage. The circuit may also include an active device coupled to the output node and a second circuit coupled to the active device and the input node. The second circuit may be configured to receive the signal and to drive the signal to the active device at a second voltage that is approximately equal to the first voltage.
摘要翻译： 电路可以包括被配置为接收信号的输入节点和被配置为耦合到负载的输出节点。 电路还可以包括耦合在输入节点和输出节点之间的第一电路。 第一电路可以被配置为接收信号并以第一电压驱动输出节点上的信号。 电路还可以包括耦合到输出节点的有源器件和耦合到有源器件和输入节点的第二电路。 第二电路可以被配置为接收信号并且以大致等于第一电压的第二电压将信号驱动到有源器件。
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公开(公告)号：US20090033426A1
公开(公告)日：2009-02-05
申请号：US11830648
申请日：2007-07-30
申请人： Jason Y. Miao
发明人： Jason Y. Miao
IPC分类号： H03F3/04
CPC分类号： H04B10/40
摘要： An amplifier stage or circuit for providing pre-emphasis. The circuit includes a first input node configured to receive a first data signal and a second input node configured to receive a second data. The circuit also includes an adjustable delay stage configured to at least partially produce a delay in the first and/or second data signals to thereby generate a first delayed signal and/or second delayed signal. The circuit additionally includes a pulse generation stage configured to generate a first pulse signal from the first delayed signal and the first data signal and/or produce a second pulse signal from the second delayed signal and the second data signal. The circuit further includes a first output node configured to output the first pulse signal and a second output node configured to output the second pulse signal.
摘要翻译： 用于提供预加重的放大器级或电路。 电路包括被配置为接收第一数据信号的第一输入节点和被配置为接收第二数据的第二输入节点。 该电路还包括可调延迟级，其被配置为至少部分地产生第一和/或第二数据信号中的延迟，从而产生第一延迟信号和/或第二延迟信号。 电路还包括脉冲发生级，被配置为从第一延迟信号和第一数据信号产生第一脉冲信号和/或从第二延迟信号和第二数据信号产生第二脉冲信号。 电路还包括被配置为输出第一脉冲信号的第一输出节点和被配置为输出第二脉冲信号的第二输出节点。
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公开(公告)号：US07626439B2
公开(公告)日：2009-12-01
申请号：US11736263
申请日：2007-05-21
申请人： Jason Y. Miao , Timothy G. Moran
发明人： Jason Y. Miao , Timothy G. Moran
IPC分类号： H03K5/08
CPC分类号： H04B10/40
摘要： An amplifier stage or circuit for providing cross-point adjustment. The circuit may include a first input node configured to receive a first data signal and a second input node configured to receive a second data signal that is complementary of the first data signal. The circuit also includes a programmable first stage having a first node coupled to the first input node and a second node coupled to the second input node that is configured to adjust an amount of current provided to the first and second data signals to create a signal offset. The circuit further includes a second stage having a first node coupled to a third node of the programmable first stage and a second node coupled to a fourth node of the programmable first stage configured to provide the signal offset at a third and fourth node of the second stage to adjust the cross-point of the first and second signals.
摘要翻译： 用于提供交叉点调整的放大器级或电路。 电路可以包括被配置为接收第一数据信号的第一输入节点和被配置为接收与第一数据信号互补的第二数据信号的第二输入节点。 电路还包括可编程第一级，其具有耦合到第一输入节点的第一节点和耦合到第二输入节点的第二节点，其被配置为调整提供给第一和第二数据信号的电流量，以产生信号偏移 。 电路还包括第二级，其具有耦合到可编程第一级的第三节点的第一节点和耦合到可编程第一级的第四节点的第二节点，其被配置为在第二节点的第三和第四节点处提供信号偏移 阶段来调整第一和第二信号的交叉点。
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公开(公告)号：US07860407B2
公开(公告)日：2010-12-28
申请号：US11830648
申请日：2007-07-30
申请人： Jason Y. Miao
发明人： Jason Y. Miao
CPC分类号： H04B10/40
摘要： An amplifier stage or circuit for providing pre-emphasis. The circuit includes a first input node configured to receive a first data signal and a second input node configured to receive a second data. The circuit also includes an adjustable delay stage configured to at least partially produce a delay in the first and/or second data signals to thereby generate a first delayed signal and/or second delayed signal. The circuit additionally includes a pulse generation stage configured to generate a first pulse signal from the first delayed signal and the first data signal and/or produce a second pulse signal from the second delayed signal and the second data signal. The circuit further includes a first output node configured to output the first pulse signal and a second output node configured to output the second pulse signal.
摘要翻译： 用于提供预加重的放大器级或电路。 电路包括被配置为接收第一数据信号的第一输入节点和被配置为接收第二数据的第二输入节点。 该电路还包括可调延迟级，其被配置为至少部分地产生第一和/或第二数据信号中的延迟，从而产生第一延迟信号和/或第二延迟信号。 电路还包括脉冲发生级，被配置为从第一延迟信号和第一数据信号产生第一脉冲信号和/或从第二延迟信号和第二数据信号产生第二脉冲信号。 电路还包括被配置为输出第一脉冲信号的第一输出节点和被配置为输出第二脉冲信号的第二输出节点。
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公开(公告)号：US20080074196A1
公开(公告)日：2008-03-27
申请号：US11697175
申请日：2007-04-05
申请人： Jason Y. Miao
发明人： Jason Y. Miao
IPC分类号： H03F3/08
CPC分类号： H04L25/085
摘要： An amplifier output stage for reducing Electromagnetic Interference (EMI) that includes an output node and an input node. A first transistor has a base terminal coupled to the input node and has a collector terminal coupled to the output node. A second transistor has a base terminal coupled to an emitter terminal of the first transistor and has a collector terminal coupled to the output node. A third transistor has a collector terminal coupled to the emitter terminal of the first transistor and the base of the second transistor and has an emitter terminal coupled to a current source and to an emitter terminal of the second transistor. A resistor has a first terminal coupled to a base terminal of the third transistor and has a second terminal coupled to the emitter terminal of the first transistor.
摘要翻译： 放大器输出级，用于减少包括输出节点和输入节点的电磁干扰（EMI）。 第一晶体管具有耦合到输入节点的基极，并且具有耦合到输出节点的集电极端子。 第二晶体管具有耦合到第一晶体管的发射极端子的基极端子，并且具有耦合到输出节点的集电极端子。 第三晶体管具有耦合到第一晶体管的发射极端子和第二晶体管的基极的集电极端子，并且具有耦合到电流源和第二晶体管的发射极端子的发射极端子。 电阻器具有耦合到第三晶体管的基极端子的第一端子，并且具有耦合到第一晶体管的发射极端子的第二端子。
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公开(公告)号：US08896357B2
公开(公告)日：2014-11-25
申请号：US13464286
申请日：2012-05-04
申请人： Jason Y. Miao
发明人： Jason Y. Miao
CPC分类号： H04L7/0079 , H03L7/087 , H04L7/033 , H04L25/03057
摘要： A system may include a clock and data recovery circuit that includes one or more analog components. The system may also include a digital control circuit configured to control the clock and data recovery circuit. The digital control circuit and the clock and data recovery circuit may be formed on a single substrate.
摘要翻译： 系统可以包括包括一个或多个模拟组件的时钟和数据恢复电路。 该系统还可以包括配置成控制时钟和数据恢复电路的数字控制电路。 数字控制电路和时钟数据恢复电路可以形成在单个基板上。
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