公开(公告)号：US07231152B2

公开(公告)日：2007-06-12

申请号：US10404966

申请日：2003-04-01

Applicant: Suk Ki Kim ,  Joon Jea Sung ,  Geun Soon Kang

Inventor： Suk Ki Kim ,  Joon Jea Sung ,  Geun Soon Kang

IPC: H04B10/06

CPC classification number: G08C23/04

Abstract: Disclosed is an infrared remote control receiver comprising a photo diode for converting an optical signal to an electrical signal, a semiconductor signal processing device for receiving the electrical from the photo diode, eliminating noise components from the electrical signal output from the photo diode and generating a pulse signal corresponding to a remote control signal transmitted from a remote control transmission device, and a micro computer for receiving the pulse signal from the semiconductor signal processing device and performing a remote control operation instructed by a user of the remote control transmission device by decoding the received pulse signal, wherein the semiconductor signal processing device is fabricated using CMOS devices fabrication processes.

Abstract translation: 公开了一种红外遥控接收器，其包括用于将光信号转换为电信号的光电二极管，用于从光电二极管接收电的半导体信号处理装置，消除从光电二极管输出的电信号的噪声分量， 对应于从远程控制传输设备发送的远程控制信号的脉冲信号;以及微计算机，用于从半导体信号处理设备接收脉冲信号，并且执行远程控制传输设备的用户指示的遥控操作， 接收脉冲信号，其中使用CMOS器件制造工艺制造半导体信号处理器件。

公开(公告)号：US5923183A

公开(公告)日：1999-07-13

申请号：US826509

申请日：1997-04-03

Applicant: Seong-Won Kim ,  Min-Kyu Song ,  Eu-Ro Joe ,  Geun-Soon Kang

Inventor： Seong-Won Kim ,  Min-Kyu Song ,  Eu-Ro Joe ,  Geun-Soon Kang

IPC: G11C11/417 ,  G11C7/00 ,  G11C11/409 ,  H03K17/16 ,  H03K17/687 ,  H03K19/003 ,  H03K19/0175 ,  H03K19/0948 ,  H03K19/0185

CPC classification number: H03K19/00361

Abstract: A CMOS output buffer circuit includes a predriving circuit which generates two predriving signals, a main driving circuit which has a plurality of parallel connected pull-up transistors and a plurality of parallel connected pull-down transistors, and a sequential driving circuit which provides sequential pull-up and pull-down driving signals to the pull-up and pull-down transistors, respectively. The main driving circuit generates the output signal according to the sequential pull-up or pull-down driving signals, whereby the output signal is developed step by step into either the power supply potential or the ground potential. In the manner, any spike in the switching current is considerably mitigated, thereby reducing switching noise.

Abstract translation: CMOS输出缓冲电路包括产生两个预取信号的预制电路，具有多个并联连接的上拉晶体管的主驱动电路和多个并联的下拉晶体管，以及顺序驱动电路，其提供顺序拉 上拉和下拉驱动信号分别到上拉和下拉晶体管。 主驱动电路根据顺序上拉或下拉驱动信号产生输出信号，从而将输出信号逐步展开到电源电位或地电位。 以这种方式，开关电流中的任何尖峰都被大大减轻，从而降低开关噪声。

公开(公告)号：US6052025A

公开(公告)日：2000-04-18

申请号：US124599

申请日：1998-07-29

Applicant: Dong-Young Chang ,  You-Mi Lee ,  Seung-Hoon Lee ,  Geun-Soon Kang ,  Hee-Cheol Choi

Inventor： Dong-Young Chang ,  You-Mi Lee ,  Seung-Hoon Lee ,  Geun-Soon Kang ,  Hee-Cheol Choi

IPC: H01L21/8234 ,  H01L27/088 ,  H03F3/45

CPC classification number: H03F3/45219 ,  H03F3/45654 ,  H03F2203/45398

Abstract: Operational amplifier integrated circuits include a differential input stage, a cascode current mirror, a cascode current source and a preferred bias signal generator which is responsive to a clock signal and is electrically coupled to the differential input stage, the cascode current mirror and the cascode current source. This preferred bias signal generator sequentially enables the cascode current mirror and then the differential input stage in response to a rising edge of the clock signal and disables the cascode current mirror and the cascode current source in response to a falling edge of the clock signal. This sequential enablement of the cascode current mirror before the differential input stage improves the unity gain phase margin characteristics of the circuit and the disablement of the cascode current mirror and the cascode current source in response to the falling edge of the clock signal decreases the power consumption requirements of the circuit.

Abstract translation: 运算放大器集成电路包括差分输入级，共源共栅电流镜，共源共栅电流源和优选的偏置信号发生器，其响应于时钟信号并电耦合到差分输入级，共源共栅电流镜和共源共栅电流 资源。 该优选的偏置信号发生器响应于时钟信号的上升沿而依次启用共源共栅电流镜和差分输入级，并响应时钟信号的下降沿禁用共源共栅电流反射镜和共源共栅电流源。 在差分输入级之前，级联电流镜的这种顺序启用提高了电路的单位增益相位裕度特性，并且响应于时钟信号的下降沿，共源共栅电流反射镜和共源共栅电流源的禁用降低了功耗 电路要求。

公开(公告)号：US06563364B2

公开(公告)日：2003-05-13

申请号：US10044039

申请日：2002-01-11

Applicant: Jin-kuk Lee ,  Dong-young Chang ,  You-jin Cha ,  Geun-soon Kang ,  Seung-hoon Lee

Inventor： Jin-kuk Lee ,  Dong-young Chang ,  You-jin Cha ,  Geun-soon Kang ,  Seung-hoon Lee

IPC: G06F764

CPC classification number: H03G1/0094 ,  G06G7/06 ,  G06J1/00

Abstract: A gain controller using switched capacitors is provided. The gain controller is operable in a sampling mode or an amplifying mode and controls the gain of an analog input signal. The gain controller includes an operational amplifier, input capacitors, a feedback capacitor, and switches. The operational amplifier controls the gain of the analog input signal and generates an output signal having the controlled gain. The input capacitors are connected to the input side of the operational amplifier in parallel. The feedback capacitor is connected between the input side and the output side of the operational amplifier. The switches connect at least one of the input capacitors to the input signal or a reference voltage, in response to the kinds of operation modes and a predetermined externally applied digital gain control signal. According to the gain controller using switched capacitors, it is possible to automatically control the gain of an input signal at high speed and to reduce power consumption since the time required for settling the gain of the input signal to a desired value is short.

公开(公告)号：US06388500B1

公开(公告)日：2002-05-14

申请号：US09575994

申请日：2000-05-23

Applicant: Jin-kuk Lee ,  Dong-young Chang ,  You-jin Cha ,  Geun-soon Kang ,  Seung-hoon Lee

Inventor： Jin-kuk Lee ,  Dong-young Chang ,  You-jin Cha ,  Geun-soon Kang ,  Seung-hoon Lee

IPC: G06G718

CPC classification number: H03G1/0094 ,  G06G7/06 ,  G06J1/00

Abstract: A gain controller using switched capacitors is provided. The gain controller is operable in a sampling mode or an amplifying mode and controls the gain of an analog input signal. The gain controller includes an operational amplifier, input capacitors, a feedback capacitor, and switches. The operational amplifier controls the gain of the analog input signal and generates an output signal having the controlled gain. The input capacitors are connected to the input side of the operational amplifier in parallel. The feedback capacitor is connected between the input side and the output side of the operational amplifier. The switches connect at least one of the input capacitors to the input signal or a reference voltage, in response to the kinds of operation modes and a predetermined externally applied digital gain control signal. According to the gain controller using switched capacitors, it is possible to automatically control the gain of an input signal at high speed and to reduce power consumption since the time required for settling the gain of the input signal to a desired value is short.

公开(公告)号：US6121797A

公开(公告)日：2000-09-19

申请号：US117602

申请日：1999-02-09

Applicant: Min-Kyu Song ,  Geun-Soon Kang ,  Seong-Won Kim ,  Eu-Ro Joe

Inventor： Min-Kyu Song ,  Geun-Soon Kang ,  Seong-Won Kim ,  Eu-Ro Joe

IPC: G06F7/501 ,  G06F7/50 ,  H03K19/00 ,  H03K19/0948 ,  H03K19/20

CPC classification number: G06F7/5016 ,  H03K19/0013 ,  H03K19/0948 ,  G06F2207/4816

Abstract: Disclosed is an energy economized pass-transistor logic having a level restoration circuit (50) free from leakage and a full adder using the same. The logic comprises a functional block (10) having a plurality of n type FETs (M1 . . . M4), for performing at least one logical function of inputs (12, 14, 16, 18) to generate two complementary signals (20, 22), the complementary signals (20, 22) being a weak high level signal and a strong low level signal; and a level restoration block (50) having first and second CMOS inverters (52, 54), for restoring the weak high level signal to a strong or full high level signal and preventing a leakage current flowing through one of the first and the second CMOS inverters (52, 54) where the weak high level is applied.

Abstract translation: PCT No.PCT / KR97 / 00018 Sec。 371日期1999年2月9日 102（e）1999年2月9日PCT 1997年1月30日PCT PCT。 公开号WO97 / 28604 日期1997年8月7日公开是具有电平恢复电路（50）和无全部加法器的能量节省型传输晶体管逻辑。 逻辑包括具有多个n型FET（M1 ... M4）的功能块（10），用于执行输入（12,14,16,18）的至少一个逻辑功能以产生两个互补信号（20， 22），互补信号（20,22）是弱高电平信号和强低电平信号; 以及具有第一和第二CMOS反相器（52,54）的电平恢复块（50），用于将弱高电平信号恢复到强或全高电平信号，并防止流过第一和第二CMOS中的一个的漏电流 其中施加弱高电平的逆变器（52,54）。

公开(公告)号：US5952952A

公开(公告)日：1999-09-14

申请号：US097935

申请日：1998-06-16

Applicant: Hee-Cheol Choi ,  Geun-Soon Kang

Inventor： Hee-Cheol Choi ,  Geun-Soon Kang

IPC: H01L27/04 ,  H01L21/822 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/08 ,  H03M1/12

CPC classification number: H01L27/0805

Abstract: A binary-weighted capacitor array is applicable for use in analog-to-digital or digital-to-analog converters, switched-capacitor filters, etc. A plurality of unit capacitors are arranged in a lateral row. The row is laid out in parallel to a switch array so that each metal interconnect between a unit capacitor and a corresponding switch is of a uniform length. This layout eliminates several limitations commonly found in capacitor arrays, including: top-plate parasitic error due to metal interconnections and metal overlap; ratio error due to oxide thickness gradients; and edge-definition errors.

Abstract translation: 二进制加权电容器阵列适用于模拟数字或数模转换器，开关电容滤波器等。多个单元电容器布置在横向行中。 该行与开关阵列平行布置，使得单元电容器和相应开关之间的每个金属互连具有均匀的长度。 该布局消除了电容器阵列中常见的几个限制，包括：由于金属互连和金属重叠引起的顶板寄生误差; 比例误差由于氧化物厚度梯度; 和边缘定义错误。