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公开(公告)号：US07737795B2
公开(公告)日：2010-06-15
申请号：US11946932
申请日：2007-11-29
CPC分类号： H03K3/0322 , H03K2005/00026 , H03K2005/00208 , H03K2005/00234
摘要： A ring oscillator based voltage controlled oscillator (VCO) is disclosed. The VCO includes a set of delay cells connected to each other in a ring configuration. Each of the delay cells includes a source-coupled input transistor pair, a current-steering transistor pair and a pair of load resistors. The source-coupled input transistor pair receives a pair of differential voltage inputs. The load resistors, which are connected to the source-coupled input transistor pair, provide a pair of differential voltage outputs. The current-steering transistor pair, which is connected to the source-coupled input transistor pair, receives a pair of differential bias voltage inputs. The output frequency of the VCO is directly proportional to the differential bias voltages at the pair of differential bias voltage inputs.
摘要翻译： 公开了一种基于环形振荡器的压控振荡器（VCO）。 VCO包括以环形配置彼此连接的一组延迟单元。 每个延迟单元包括源极耦合输入晶体管对，导流晶体管对和一对负载电阻。 源极耦合输入晶体管对接收一对差分电压输入。 连接到源极耦合输入晶体管对的负载电阻提供一对差分电压输出。 连接到源极耦合输入晶体管对的导流晶体管对接收一对差分偏置电压输入。 VCO的输出频率与差分偏置电压输入对的差分偏置电压成正比。
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公开(公告)号：US08093985B1
公开(公告)日：2012-01-10
申请号：US12242926
申请日：2008-10-01
申请人： Lokesh Kumath , Giri N. K. Rangan
发明人： Lokesh Kumath , Giri N. K. Rangan
IPC分类号： H01C13/00
CPC分类号： H03M1/0604 , H03M1/765
摘要： Circuits, methods, and apparatus that provide highly accurate DCPs. One example provides a DCP that includes a resistor string having taps that may be selected by a corresponding number of switches under the control of a digital word. To compensate for parasitic switch resistances and for variations in the values of the resistor sting caused by processing tolerances, a voltage-controlled resistor (VCR) is placed in parallel with the resistor string and switches. A control voltage generated using a control loop adjusts the parallel VCR such that the resistance seen across the DCP is the desired value. The control loop compares a reference resistor to loop components that are scaled to the resistor string, switches, and VCR. The reference resistor may be an external resistor or an internal resistor. If the resistor is internal, it may be trimmed, for example with lasers or fuses.
摘要翻译： 提供高精度DCP的电路，方法和设备。 一个例子提供一种DCP，其包括具有可在数字字控制下由对应数量的开关选择的抽头的电阻串。 为了补偿寄生开关电阻以及由于处理公差引起的电阻极限值的变化，压控电阻（VCR）与电阻串和开关并联放置。 使用控制回路产生的控制电压调节并行VCR，使得跨DCP看到的电阻是期望值。 控制回路将参考电阻与缩放到电阻串，开关和VCR的环路元件进行比较。 参考电阻可以是外部电阻或内部电阻。 如果电阻器是内部的，则可以使用激光器或熔断器进行修整。
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3.发明授权Signal processing system with baseband noise modulation and noise fold back reduction 有权信号处理系统，具有基带噪声调制和噪声折回公开(公告)号：US06842486B2
公开(公告)日：2005-01-11
申请号：US10425285
申请日：2003-04-29
CPC分类号： H03M3/34 , H03F1/02 , H03F1/26 , H03F3/211 , H03F3/217 , H03F3/2175 , H03F3/38 , H03F2200/331 , H03M3/50
摘要： A digital-to-analog converter (“DAC”) system utilizes chopping modulation technology to remove 1/f and other baseband noise from a baseband of a signal of interest. Chopping modulation and demodulation circuitry of the DAC operate at a chopping frequency equal to approximately one-half of a digital input signal sampling frequency. Chopping at one-half the sampling frequency allows fold back into the baseband of the input signal's frequency components and reduces fold back of noise, such as quantization noise, residing outside the baseband. In a further embodiment, a notch filter attenuates signals having frequencies around the chopping frequency prior to chopping to reduce fold back of noise into the baseband due to parasitic modulation. Coordination of chopping timing also reduces noises in the output of the DAC system.
摘要翻译： 数模转换器（“DAC”）系统利用斩波调制技术从感兴趣信号的基带去除1 / f和其他基带噪声。 DAC的斩波调制和解调电路以等于数字输入信号采样频率的大约一半的斩波频率工作。 以采样频率的一半斩波允许折回到输入信号的频率分量的基带，并减少驻留在基带外的诸如量化噪声的噪声的折返。 在另一实施例中，陷波滤波器在斩波之前衰减具有围绕斩波频率的频率的信号，以减少由于寄生调制而导致的基带的噪声折回。 斩波定时的协调还可以减少DAC系统输出的噪声。
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4.发明授权Methods and systems for compression, storage, and generation of digital filter coefficients 有权用于压缩，存储和生成数字滤波器系数的方法和系统公开(公告)号：US08271567B2
公开(公告)日：2012-09-18
申请号：US12210116
申请日：2008-09-12
申请人： Santosh Nene , Giri N. K. Rangan
发明人： Santosh Nene , Giri N. K. Rangan
IPC分类号： G06F17/10
CPC分类号： H03H17/0227
摘要： A method and system for compressing coefficients of a digital filter is provided. In one approach, the method comprises providing a digital filter having a plurality of consecutive filter coefficients including a first filter coefficient, determining consecutive difference values between each of the consecutive filter coefficients, and storing the first filter coefficient and the consecutive difference values in a memory. The consecutive filter coefficients are generated by retrieving the first filter coefficient, and adding a first difference value to the first filter coefficient to generate a consecutive second filter coefficient. The first difference value corresponds to a difference between the first filter coefficient and the second filter coefficient. A consecutive next difference value is then added to the second filter coefficient to generate a consecutive next filter coefficient. The consecutive next difference value corresponds to a difference between the second filter coefficient and the consecutive next filter coefficient.
摘要翻译： 提供了一种用于压缩数字滤波器的系数的方法和系统。 在一种方法中，该方法包括提供具有包括第一滤波器系数的多个连续滤波器系数的数字滤波器，确定每个连续滤波器系数之间的连续差值，并将第一滤波器系数和连续差值存储在存储器中 。 通过检索第一滤波器系数并将第一差值与第一滤波器系数相加以产生连续的第二滤波器系数来生成连续滤波器系数。 第一差分值对应于第一滤波器系数和第二滤波器系数之间的差。 然后将连续的下一个差值加到第二滤波器系数，以产生连续的下一个滤波器系数。 连续的下一个差值对应于第二滤波器系数和连续的下一个滤波器系数之间的差。
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公开(公告)号：US07786912B2
公开(公告)日：2010-08-31
申请号：US11999256
申请日：2007-12-03
申请人： Giri N K Rangan , Roger Levinson , John M Caruso
发明人： Giri N K Rangan , Roger Levinson , John M Caruso
IPC分类号： H03M3/00
摘要： A sigma delta converter system and method includes a multi bit quantizer circuit coupled to an output of the converter. A single bit analog-to-digital converter circuit is contained in a feedback path of the converter. The converter includes a feed forward path operable to multiply an input voltage by a feed forward coefficient having a value that is a function of a gain control input signal. The gain control input signal can have a value that is a function of the output of the multi bit quantizer.
摘要翻译： Σ-Δ转换器系统和方法包括耦合到转换器的输出端的多位量化器电路。 单个位模数转换器电路包含在转换器的反馈路径中。 该转换器包括前馈路径，其可操作以将输入电压乘以具有作为增益控制输入信号的函数的值的前馈系数。 增益控制输入信号可以具有作为多位量化器的输出的函数的值。
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6.发明授权Method and apparatus for providing multiple channel audio in a computing system 有权用于在计算系统中提供多声道音频的方法和装置公开(公告)号：US06885900B1
公开(公告)日：2005-04-26
申请号：US09613344
申请日：2000-07-10
摘要： A method and apparatus for providing multiple channel audio in a computing system includes processing that begins by receiving an audio setup signal that indicates whether audio is to be outputted as stereo audio or multiple channel audio. When multiple channel audio is to be outputted, the line-in driver is disabled in the audio processing circuitry and the multiple channel driver of the audio processing circuitry is enabled. Thus, the multiple channel driver is operably coupled to the line-in audio jack. When the audio output is to be outputted as stereo audio, the multiple channel driver is disabled and the line-in driver is enable. Thus, the line-in driver is operably coupled to the line-in audio jack.
摘要翻译： 一种用于在计算系统中提供多声道音频的方法和装置包括通过接收音频设置信号开始的处理，该音频设置信号指示音频是要作为立体声还是多声道音频输出。 当要输出多声道音频时，音频处理电路中的线路输入驱动器被禁用，音频处理电路的多通道驱动器被使能。 因此，多通道驱动器可操作地耦合到线路输入音频插孔。 当音频输出作为立体声音频输出时，多声道驱动器被禁用，并且线路输入驱动器被使能。 因此，线路输入驱动器可操作地耦合到线路输入音频插孔。
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7.发明授权公开(公告)号：US06861968B2
公开(公告)日：2005-03-01
申请号：US10668397
申请日：2003-09-23
CPC分类号： H03M7/3006 , H03M3/344 , H03M3/50 , H03M7/3026
摘要： A digital-to-analog converter (“DAC”) system utilizes notch filters and chopping modulation technology to remove l/f and other baseband noise from a baseband of a signal of interest. Chopping modulation and demodulation circuitry of the DAC operate at a chopping frequency and all harmonics equal to approximately one-half of a digital input signal sampling frequency. A notch filter attenuates signals having frequencies around the chopping frequency prior to chopping to reduce fold back of noise into the baseband due to parasitic modulation. Another notch filter attenuating signals having frequencies around twice the chopping frequency further reduces fold back of noise into the baseband.
摘要翻译： 数模转换器（“DAC”）系统利用陷波滤波器和斩波调制技术从感兴趣信号的基带去除l / f和其他基带噪声。 DAC的斩波调制和解调电路工作在斩波频率，所有谐波等于数字输入信号采样频率的大约一半。 陷波滤波器在斩波之前衰减具有围绕斩波频率的频率的信号，以减少由于寄生调制而将噪声折回到基带。 衰减具有大约斩波频率两倍的频率的信号的另一个陷波滤波器进一步降低了噪声向基带的折回。
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