利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

15 条记录 (耗时 0.013 秒)

    Semiconductor-on-insulator device interconnects
    2.
    发明授权
    Semiconductor-on-insulator device interconnects 失效
    绝缘体上半导体器件互连

    公开(公告)号：US5587597A

    公开(公告)日：1996-12-24

    申请号：US728917

    申请日：1991-07-11

    申请人： Ronald E. Reedy ,  Graham A. Garcia ,  Isaac Lagnado

    发明人： Ronald E. Reedy ,  Graham A. Garcia ,  Isaac Lagnado

    IPC分类号： H01L21/768 ,  H01L21/86 ,  H01L23/482 ,  H01L27/12 ,  H01L29/04 ,  H01L31/0392 ,  H01L31/062

    CPC分类号： H01L23/4825 ,  H01L21/76889 ,  H01L21/86 ,  H01L2924/0002 ,  Y10S148/019 ,  Y10S148/147

    摘要： A process for developing conductive interconnect regions between integrated circuit semiconductor devices formed on an insulating substrate utilizes the semiconductor material itself for formation of device interconnect regions.A patterned layer of semiconductor material is formed directly on the surface of an insulating substrate. The patterned layer includes regions where semiconductor devices are to be formed and regions which are to be used to interconnect terminals of predetermined ones of the semiconductor devices. After forming the semiconductor devices in selected regions of the semiconductor material, the regions of the semiconductor material patterned for becoming interconnects are converted to a metallic compound of the semiconductor material.

    摘要翻译： 在绝缘基板上形成的集成电路半导体器件之间形成导电互连区域的工艺利用半导体材料本身形成器件互连区域。 半导体材料的图案层直接形成在绝缘基板的表面上。 图案化层包括要形成半导体器件的区域以及用于互连预定半导体器件的端子的区域。 在半导体材料的选定区域中形成半导体器件之后，图案化成互连的半导体材料的区域被转换为半导体材料的金属化合物。

    Process for making semiconductor-on-insulator device interconnects
    3.
    发明授权
    Process for making semiconductor-on-insulator device interconnects 失效
    绝缘体上半导体器件互连

    公开(公告)号：US5066613A

    公开(公告)日：1991-11-19

    申请号：US380175

    申请日：1989-07-13

    申请人： Ronald E. Reedy ,  Graham A. Garcia ,  Isaac Lagnado

    发明人： Ronald E. Reedy ,  Graham A. Garcia ,  Isaac Lagnado

    IPC分类号： H01L21/768 ,  H01L21/86 ,  H01L23/482

    CPC分类号： H01L23/4825 ,  H01L21/76889 ,  H01L21/86 ,  H01L2924/0002 ,  Y10S148/019 ,  Y10S148/147

    摘要： A process for developing conductive interconnect regions between integrated circuit semiconductor devices formed on an insulating substrate utilizes the semiconductor material itself for formation of device interconnect regions.A patterned layer of semiconductor material is formed directly on the surface of an insulating substrate. The patterned layer includes regions where semiconductor devices are to be formed and regions which are to be used to interconnect terminals of predetermined ones of the semiconductor devices. After forming the semiconductor devices in selected regions of the semiconductor material, the regions of the semiconductor material patterned for becoming interconnects are converted to a metallic compound of the semiconductor material.

    摘要翻译： 在绝缘基板上形成的集成电路半导体器件之间形成导电互连区域的工艺利用半导体材料本身形成器件互连区域。 半导体材料的图案层直接形成在绝缘基板的表面上。 图案化层包括要形成半导体器件的区域以及用于互连预定半导体器件的端子的区域。 在半导体材料的选定区域中形成半导体器件之后，图案化成互连的半导体材料的区域被转换为半导体材料的金属化合物。

    Dual polarity floating gate MOS analog memory device
    4.
    发明授权
    Dual polarity floating gate MOS analog memory device 失效
    双极性浮栅MOS模拟存储器件

    公开(公告)号：US5027171A

    公开(公告)日：1991-06-25

    申请号：US405498

    申请日：1989-08-28

    申请人： Ronald E. Reedy ,  Randy L. Shimabukuro ,  Graham A. Garcia

    发明人： Ronald E. Reedy ,  Randy L. Shimabukuro ,  Graham A. Garcia

    IPC分类号： G11C27/00 ,  H01L27/115

    CPC分类号： G11C27/005 ,  H01L27/115

    摘要： A dual-polarity nonvolatile MOS analog memory cell is disclosed that comprises two pairs of complementary metal oxide field effect transistors. Each pair includes a p-channel and an n-channel transistor. The gates of each transistor are all operably coupled in common to form a common floating gate. The sources of the transistors of the first transistor pair are operably coupled to a common ground. The sources of the second pair of transistors are operably coupled together to form an output junction. Positive voltage applied to the drain of the n-channel transistor of the first transistor pair causes a positive analog value to be stored in memory when there previously was no value stored in memory, or increases a value previously stored in memory. Negative voltage applied to the drain of the p-channel transistor of the first transistor pair causes a negative analog value to be stored in memory when there previously was no value stored in memory, or decreases a value previously stored in memory.

    摘要翻译： 公开了一种双极性非易失性MOS模拟存储单元，其包括两对互补金属氧化物场效应晶体管。 每对包括一个p沟道和一个n沟道晶体管。 每个晶体管的栅极共同操作耦合以形成公共的浮置栅极。 第一晶体管对的晶体管的源极可操作地耦合到公共地。 第二对晶体管的源极可操作地耦合在一起以形成输出结。 施加到第一晶体管对的n沟道晶体管的漏极的正电压在先前没有存储在存储器中的值时将正模拟值存储在存储器中，或者增加先前存储在存储器中的值。 施加到第一晶体管对的p沟道晶体管的漏极的负电压在先前没有存储在存储器中的值时将负模拟值存储在存储器中，或者减小先前存储在存储器中的值。

    Thin-film integrated injection logic
    5.
    发明授权
    Thin-film integrated injection logic 失效
    薄膜集成注入逻辑

    公开(公告)号：US4843448A

    公开(公告)日：1989-06-27

    申请号：US183965

    申请日：1988-04-18

    申请人： Graham A. Garcia ,  Ronald E. Reedy

    发明人： Graham A. Garcia ,  Ronald E. Reedy

    IPC分类号： H01L27/02 ,  H01L27/12

    CPC分类号： H01L27/12 ,  H01L27/0233

    摘要： An integrated injection logic device formed on an insulating substrate. A lateral, load transistor and an adjacent, vertical switching transistor are formed in the semiconductor layer such that the collector region of the lateral transistor coincides with the base region of the switching transistor. The emitter of the switching transistor is located at the surface of the semiconductor injecting carriers downward into the collector. Isolated multiple collector contacts required for wired-AND logic are obtained by using separate Schottky-barrier contacts for each collector output.

    摘要翻译： 形成在绝缘基板上的集成注入逻辑器件。 在半导体层中形成横向负载晶体管和相邻的垂直开关晶体管，使得横向晶体管的集电极区域与开关晶体管的基极区域重合。 开关晶体管的发射极位于半导体注入载体的表面，向下进入集电极。 通过为每个集电极输出使用单独的肖特基势垒触点，可以获得线对和逻辑所需的隔离多个集电极触点。

    Triple base bipolar phototransistor
    6.
    发明授权
    Triple base bipolar phototransistor 失效
    三基极双极光电晶体管

    公开(公告)号：US06703647B1

    公开(公告)日：2004-03-09

    申请号：US10131442

    申请日：2002-04-22

    申请人： Graham A. Garcia ,  George P. Imthurn

    发明人： Graham A. Garcia ,  George P. Imthurn

    IPC分类号： H01L310328

    CPC分类号： H01L31/1105

    摘要： A high gain phototransistor uses lateral and vertical transistor structures and a triple base. The base regions of two vertical structures are in the bulk of a semiconductor substrate while the base of a single lateral structure is adjacent a light receiving phototransistor surface. Minority carrier generation extends from the base region of the lateral transistor to the base regions of the vertical transistors and is present in the vertical regions within a diffusion length of the optically generated carriers of the lateral base. The bases of all three transistor structures are electrically connected. The collector electrodes of one of the vertical structures and the lateral structure are electrically connected, while the emitter electrodes of the other of the vertical structures and the lateral structures are electrically connected. Finally, the remaining vertical collector and emitter electrodes are electrically connected via a buried layer adjacent the phototransistor wafer substrate.

    摘要翻译： 高增益光电晶体管使用横向和垂直晶体管结构和三基极。 两个垂直结构的基极区域位于半导体衬底的主体中，而单个横向结构的基极与受光光电晶体管表面相邻。 少数载波生成从横向晶体管的基极区域延伸到垂直晶体管的基极区域，并且存在于横向基极的光学生成载流子的扩散长度内的垂直区域中。 所有三个晶体管结构的基极电连接。 垂直结构和横向结构中的一个的集电极电连接，而另一个垂直结构的发射电极和横向结构电连接。 最后，剩余的垂直集电极和发射极通过与光电晶体管晶片衬底相邻的掩埋层电连接。

    Method and apparatus for characterizing the quality of electrically thin semiconductor films
    8.
    发明授权
    Method and apparatus for characterizing the quality of electrically thin semiconductor films 失效
    用于表征电薄膜半导体膜质量的方法和装置

    公开(公告)号：US5196802A

    公开(公告)日：1993-03-23

    申请号：US516492

    申请日：1990-04-23

    申请人： Mark L. Burgener ,  Graham A. Garcia ,  Ronald E. Reedy

    发明人： Mark L. Burgener ,  Graham A. Garcia ,  Ronald E. Reedy

    IPC分类号： G01R31/28

    CPC分类号： G01R31/2831

    摘要： A method and apparatus for characterizing the quality of an electrically thin semiconductor film and its interfaces with adjacent materials by employing a capacitor and a topside electrical contact on the same side of the electrically thin semiconductor film to thereby permit the taking of capacitance-voltage (C-V) measurements. A computer controlled C-V measuring system is operatively coupled to the contact and capacitor to modulate the potential on the capacitor. Variation of the voltage applied to the capacitor enables modulation of the potential applied to the film to thereby vary the conductivity of the film between the capacitor gate node and the topside contact.

    摘要翻译： 一种用于通过在电薄膜半导体膜的同一侧上采用电容器和顶侧电接触来表征电薄半导体膜的质量及其与相邻材料的界面的方法和装置，从而允许采用电容电压（CV ） 测量。 计算机控制的C-V测量系统可操作地耦合到触点和电容器以调制电容器上的电位。 施加到电容器的电压的变化使得能够调制施加到膜的电位，从而改变电容器栅极节点和顶侧触点之间的膜的导电性。

    Method for forming low and high minority carrier lifetime layers in a single semiconductor structure
    10.
    发明授权
    Method for forming low and high minority carrier lifetime layers in a single semiconductor structure 失效
    在单个半导体结构中形成低和高的少数载流子寿命层的方法

    公开(公告)号：US5468674A

    公开(公告)日：1995-11-21

    申请号：US260155

    申请日：1994-06-08

    申请人： Howard W. Walker ,  Graham A. Garcia

    发明人： Howard W. Walker ,  Graham A. Garcia

    IPC分类号： H01L21/20 ,  H01L21/76

    CPC分类号： H01L21/2007 ,  Y10S148/012 ,  Y10S148/15

    摘要： A method for forming a semiconductor structure having a layer of low minority carrier lifetime and a layer of high minority carrier lifetime comprises the steps of forming a silicon dioxide layer on a layer of low minority carrier lifetime silicon of a silicon-on-sapphire handle wafer and another layer of silicon dioxide on a layer of high minority carrier lifetime silicon of a bulk silicon device wafer. The silicon dioxide layers are placed in contact and annealed to form a bonded structure having an annealed layer of silicon dioxide. The layer of bulk silicon is then thinned. The thinned layer of bulk silicon and the annealed silicon dioxide layer are patterned by photolithography to form mesas of high minority carrier lifetime silicon and to expose regions of low minority carrier lifetime silicon on the bonded structure.

    摘要翻译： 一种用于形成具有低少数载流子寿命层和具有高少数载流子寿命的层的半导体结构的方法包括以下步骤：在蓝宝石蓝宝石处理晶片上的少数少数载流子寿命硅层上形成二氧化硅层 以及另一层二氧化硅在体硅器件晶片的高少数载流子寿命硅层上。 将二氧化硅层接触并退火以形成具有退火层的二氧化硅的结合结构。 然后将体硅层变薄。 通过光刻法将体硅和退火的二氧化硅层的薄化层图案化以形成高少数载流子寿命硅的台面并暴露粘结结构上的少数载流子寿命的硅的区域。