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    CMOS circuit including double-insulated-gate field-effect transistors
    3.
    发明授权
    CMOS circuit including double-insulated-gate field-effect transistors 失效
    CMOS电路包括双绝缘栅场效应晶体管

    公开(公告)号：US07282959B2

    公开(公告)日：2007-10-16

    申请号：US11072401

    申请日：2005-03-07

    申请人： Toshihiro Sekigawa ,  Hanpei Koike ,  Yongxun Liu ,  Meishoku Masahara

    发明人： Toshihiro Sekigawa ,  Hanpei Koike ,  Yongxun Liu ,  Meishoku Masahara

    IPC分类号： H03K19/094

    CPC分类号： H01L27/1203 ,  G11C11/412 ,  H01L27/1108

    摘要： It is an object of the present invention to provide a CMOS circuit implemented using four-terminal double-insulated-gate field-effect transistors, in which the problems described above can be overcome. Another object of the present invention is to reduce power consumption in a circuit unit that is in an idle state or ready state, i.e., to reduce static power consumption. The two gate electrodes of a P-type four-terminal double-insulated-gate field-effect transistor are electrically connected to each other and are electrically connected to one of the gate electrodes of an N-type four-terminal double-insulated-gate field-effect transistor, whereby an input terminal of a CMOS circuit is formed, and a threshold voltage of the N-type four-terminal double-insulated-gate field-effect transistor is controlled by controlling a potential of the other gate of the N-type four-terminal double-insulated-gate field-effect transistor.

    摘要翻译： 本发明的目的是提供使用四端双重绝缘栅场效应晶体管实现的CMOS电路，其中可以克服上述问题。 本发明的另一个目的是降低处于空闲状态或就绪状态的电路单元中的功耗，即减少静态功耗。 P型四端子双绝缘栅场效应晶体管的两个栅电极彼此电连接并且电连接到N型四端双绝缘栅的一个栅电极 场效应晶体管，由此形成CMOS电路的输入端子，并且通过控制N型四端子双绝缘栅极场效应晶体管的另一个栅极的电位来控制N型四端双重绝缘栅极场效应晶体管的阈值电压 型四端双绝缘栅场效应晶体管。

    CMOS circuit including double-insulated-gate field-effect transistors
    4.
    发明申请
    CMOS circuit including double-insulated-gate field-effect transistors 失效
    CMOS电路包括双绝缘栅场效应晶体管

    公开(公告)号：US20050199964A1

    公开(公告)日：2005-09-15

    申请号：US11072401

    申请日：2005-03-07

    申请人： Toshihiro Sekigawa ,  Hanpei Koike ,  Yongxun Liu ,  Meishoku Masahara

    发明人： Toshihiro Sekigawa ,  Hanpei Koike ,  Yongxun Liu ,  Meishoku Masahara

    IPC分类号： G11C11/41 ,  G11C11/412 ,  H01L21/8238 ,  H01L21/8244 ,  H01L27/092 ,  H01L27/11 ,  H01L29/76 ,  H03K19/0948

    CPC分类号： H01L27/1203 ,  G11C11/412 ,  H01L27/1108

    摘要： It is an object of the present invention to provide a CMOS circuit implemented using four-terminal double-insulated-gate field-effect transistors, in which the problems described above can be overcome. Another object of the present invention is to reduce power consumption in a circuit unit that is in an idle state or ready state, i.e., to reduce static power consumption. The two gate electrodes of a P-type four-terminal double-insulated-gate field-effect transistor are electrically connected to each other and are electrically connected to one of the gate electrodes of an N-type four-terminal double-insulated-gate field-effect transistor, whereby an input terminal of a CMOS circuit is formed, and a threshold voltage of the N-type four-terminal double-insulated-gate field-effect transistor is controlled by controlling a potential of the other gate of the N-type four-terminal double-insulated-gate field-effect transistor.

    摘要翻译： 本发明的目的是提供使用四端双重绝缘栅场效应晶体管实现的CMOS电路，其中可以克服上述问题。 本发明的另一个目的是降低处于空闲状态或就绪状态的电路单元中的功耗，即减少静态功耗。 P型四端子双绝缘栅场效应晶体管的两个栅电极彼此电连接并且电连接到N型四端双绝缘栅的一个栅电极 场效应晶体管，由此形成CMOS电路的输入端子，并且通过控制N型四端子双绝缘栅极场效应晶体管的另一个栅极的电位来控制N型四端双重绝缘栅极场效应晶体管的阈值电压 型四端双绝缘栅场效应晶体管。

    Dual-gate field effect transistor
    6.
    发明申请
    Dual-gate field effect transistor 审中-公开
    双栅场效应晶体管

    公开(公告)号：US20070029623A1

    公开(公告)日：2007-02-08

    申请号：US10580433

    申请日：2004-12-06

    申请人： Yongxun Liu ,  Meishoku Masahara ,  Kenichi Ishii ,  Toshihiro Sekigawa ,  Eiichi Suzuki

    发明人： Yongxun Liu ,  Meishoku Masahara ,  Kenichi Ishii ,  Toshihiro Sekigawa ,  Eiichi Suzuki

    IPC分类号： H01L29/76 ,  H01L21/336

    CPC分类号： H01L29/785 ,  H01L29/42384 ,  H01L29/66795

    摘要： A dual-gate field effect transistor includes a substrate 1, a source 7-1, a drain 7-2, a vertical channel 5 provided between the source and the drain as rising from the substrate, a pair of gate insulation films 6-1 and 6-2 sandwiching the channel from a direction orthogonal to a carrier-running direction in the channel and a pair of gate electrodes 3-1 and 3-2 facing the vertical channel 5, respectively, via the pair of gate insulation films 6-1 and 6-2, wherein the pair of insulation films have different thicknesses t1 and t2. It is also possible that the pair of gate insulation films 6-1 and 6-2 have different permittivities ε1 and ε2 and that the pair of gate electrodes have different work functions Φ1 and Φ2. Thus, it is possible to set the threshold voltage of the dual-gate field effect transistor to a desired value when fabricating it. Furthermore, it is possible to avoid the problem of an increase in subthreshold slope that occurs in the prior art.

    摘要翻译： 双栅场效应晶体管包括衬底1，源极7-1，漏极7-2，设置在源极和漏极之间的垂直沟道5，从衬底上升，一对栅极绝缘膜6-1 6-2夹着通道，并且通过一对栅极绝缘膜6〜6分别与沟道5的载流子行进方向正交的方向和一对面对垂直沟道5的栅电极3〜1〜3〜 1和6-2，其中一对绝缘膜具有不同的厚度t 1和t 2。也可能的是，一对栅极绝缘膜6-1和6-2具有不同的介电常数ε1和ε2，并且 一对栅电极具有不同的功函数Phi 1和Phi 2.因此，可以在制造时将双栅极场效应晶体管的阈值电压设置为期望值。 此外，可以避免在现有技术中发生的亚阈值斜率增加的问题。

    Field-effect transistor and integrated circuit including the same
    8.
    发明授权
    Field-effect transistor and integrated circuit including the same 失效
    场效应晶体管和集成电路包括相同

    公开(公告)号：US07999321B2

    公开(公告)日：2011-08-16

    申请号：US12602314

    申请日：2008-05-09

    申请人： Yongxun Liu ,  Takashi Matsukawa ,  Meishoku Masahara ,  Kazuhiko Endo ,  Shinichi Ouchi

    发明人： Yongxun Liu ,  Takashi Matsukawa ,  Meishoku Masahara ,  Kazuhiko Endo ,  Shinichi Ouchi

    IPC分类号： H01L27/12

    CPC分类号： H01L29/78609 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7853 ,  H01L29/78696

    摘要： A field-effect transistor comprising a movable gate electrode that suppresses a leakage current from the gate electrode, and has a large current drivability and a low leakage current between a source and a drain. The field-effect transistor comprises: an insulating substrate; a semiconductor layer of triangle cross-sectional shape formed on the insulating substrate, having a gate insulation film on a surface, and forming a channel in a lateral direction; fixed electrodes that are arranged adjacent to both sides of the semiconductor layer and in parallel to the semiconductor layer, each of the electrodes having an insulation film on a surface; a source/drain formed at the end part of the semiconductor layer; and the movable gate electrode formed above the semiconductor layer and the fixed electrodes with a gap.

    摘要翻译： 一种场效应晶体管，包括抑制来自栅电极的漏电流的可移动栅电极，并且在源极和漏极之间具有大的电流驱动能力和低的漏电流。 场效应晶体管包括：绝缘基板; 形成在所述绝缘基板上的三角形截面形状的半导体层，在表面上具有栅极绝缘膜，并且沿横向形成沟道; 固定电极，其布置成与半导体层的两侧相邻并且平行于半导体层，每个电极在表面上具有绝缘膜; 在半导体层的端部形成的源极/漏极; 以及形成在半导体层上方的可动栅电极和具有间隙的固定电极。

    SRAM device
    10.
    发明授权
    SRAM device 有权
    SRAM器件

    公开(公告)号：US08077510B2

    公开(公告)日：2011-12-13

    申请号：US12517696

    申请日：2007-12-06

    申请人： Shinichi Ouchi ,  Yongxun Liu ,  Meishoku Masahara ,  Takashi Matsukawa ,  Kazuhiko Endo

    发明人： Shinichi Ouchi ,  Yongxun Liu ,  Meishoku Masahara ,  Takashi Matsukawa ,  Kazuhiko Endo

    IPC分类号： G11C11/34 ,  G11C11/00

    CPC分类号： H01L27/1203 ,  G11C11/412 ,  G11C11/413 ,  H01L21/84 ,  H01L27/11 ,  H01L27/1108 ,  H01L29/785

    摘要： An SRAM device including a memory cell, the memory cell having two access transistors connected to a word line, and a flip-flop circuit having complementary transistors, the transistor being a field effect transistor having a standing semiconductor thin plate, a logic signal input gate and a bias voltage input gate, the gates sandwiching the semiconductor thin plate and being electrically separated from each other, a first bias voltage is applied to bias voltage input gates of the transistors of the memory cells in a row including a memory cell being accessed for reading or writing, and a second bias voltage is applied to the bias voltage input gates of the transistors of the memory cells in a row including a memory cell under memory holding operation.

    摘要翻译： 一种包括存储单元的SRAM器件，具有连接到字线的两个存取晶体管的存储单元以及具有互补晶体管的触发器电路，该晶体管是具有立方半导体薄板的场效应晶体管，逻辑信号输入栅极 以及偏置电压输入栅极，所述栅极夹着半导体薄板并彼此电分离，将第一偏置电压施加到存储器单元的晶体管的偏置电压输入栅极，所述存储器单元的晶体管包括被访问的存储器单元 读取或写入，并且第二偏置电压被施加到包括存储器保持操作下的存储器单元的行中的存储器单元的晶体管的偏置电压输入栅极。