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1.发明授权2T2C signal margin test mode using a defined charge exchange between BL and/BL 失效2T2C信号余量测试模式，使用BL和/ BL之间定义的电荷交换公开(公告)号：US06876590B2
公开(公告)日：2005-04-05
申请号：US10301548
申请日：2002-11-20
申请人： Hans-Oliver Joachim , Michael Jacob , Nobert Rehm
发明人： Hans-Oliver Joachim , Michael Jacob , Nobert Rehm
摘要： The present invention provides a test mode section for facilitating a worst case product test sequence for signal margin to ensure full product functionality over the entire component lifetime taking all aging effects into account. A semiconductor memory test mode configuration includes a first capacitor for storing digital data and connecting a cell plate line to a first bit line through a first select transistor. The first select transistor activated through a connection to a word line. A second capacitor stores digital data and connects the cell plate line to a second bit line through a second select transistor. The second select transistor is activated through a connection to the word line. A sense amplifier is connected to the first and second bit lines and measures a differential read signal on the first and second bit lines. A third transistor transfers charge between the first and second bit lines third to reduce the differential read signal.
摘要翻译： 本发明提供了一种测试模式部分，用于促进用于信号余量的最坏情况产品测试序列，以确保整个组件寿命期间的全部产品功能，从而考虑所有老化效应。 半导体存储器测试模式配置包括用于存储数字数据并通过第一选择晶体管将单元板线连接到第一位线的第一电容器。 通过连接到字线而激活的第一选择晶体管。 第二电容器存储数字数据，并通过第二选择晶体管将单元板线连接到第二位线。 通过与字线的连接激活第二选择晶体管。 读出放大器连接到第一和第二位线，并测量第一和第二位线上的差分读取信号。 第三晶体管在第一和第二位线之间传输电荷，以减少差分读取信号。
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公开(公告)号：US20050050261A1
公开(公告)日：2005-03-03
申请号：US10650458
申请日：2003-08-27
申请人： Thomas Roehr , Michael Jacob , Nobert Rehm , Hans-Oliver Joachim
发明人： Thomas Roehr , Michael Jacob , Nobert Rehm , Hans-Oliver Joachim
CPC分类号： G11C8/12 , G06F12/0893 , G06F2212/2022 , G06F2212/2024 , G11C16/10 , G11C2207/2245
摘要： A data storage device comprises a controller, a FeRAM memory unit, and a flash memory unit having a much higher data storage capacity than the FeRAM memory unit. Initially, when data is received by the data storage device, the controller stores it in the FeRAM memory unit. This can be done very quickly, since FeRAM devices have a high write rate. Subsequently, the controller transfers the data to the flash memory unit. Thus, the data storage device combines the high storage rate ability of FeRAM devices and the high storage capacity of flash memory devices.
摘要翻译： 数据存储装置包括控制器，FeRAM存储器单元和具有比FeRAM存储器单元高得多的数据存储容量的闪存单元。 最初，当数据存储装置接收到数据时，控制器将其存储在FeRAM存储单元中。 这可以非常快速地完成，因为FeRAM器件具有高写入速率。 随后，控制器将数据传送到闪存单元。 因此，数据存储设备结合了FeRAM器件的高存储容量和闪存器件的高存储容量。
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公开(公告)号：US07102908B2
公开(公告)日：2006-09-05
申请号：US10651753
申请日：2003-08-29
申请人： Roehr Thomas , Hans-Oliver Joachim , Nobert Rehm
发明人： Roehr Thomas , Hans-Oliver Joachim , Nobert Rehm
IPC分类号： G11C11/22
CPC分类号： G11C11/22
摘要： The present invention includes a ferro fuse cell comprising a ferroelectric storage capacitor electrically connected to a plate on one side and to a sense amplifier on the other side. A ferroelectric measurement capacitor is electrically connected between the ferroelectric storage capacitor and the sense amplifier.
摘要翻译： 本发明包括一个铁熔体单元，其包括电连接到一侧的板和另一侧的读出放大器的铁电存储电容器。 铁电测量电容器电连接在铁电存储电容器和读出放大器之间。
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公开(公告)号：US06885597B2
公开(公告)日：2005-04-26
申请号：US10065011
申请日：2002-09-10
CPC分类号： G11C29/50 , G11C11/22 , G11C2029/1204 , G11C2029/5004
摘要： A test circuit for testing differential read signals during a memory access is disclosed. The test circuit is coupled to a pair of bit lines. During a read access, a selected memory cell produces a differential read signal on the bit lines. When the test circuit is activated, the magnitude of the differential read signal is varied. This enables easy testing of read signal margins in, for example, memory ICs.
摘要翻译： 公开了一种用于在存储器访问期间测试差分读取信号的测试电路。 测试电路耦合到一对位线。 在读访问期间，所选存储单元在位线上产生差分读信号。 当测试电路被激活时，差分读取信号的幅度是变化的。 这使得能够容易地测试例如存储器IC中的读取信号余量。
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5.发明申请Signal margin test mode for FeRAM with ferroelectric reference capacitor 审中-公开具有铁电参考电容的FeRAM的信号余量测试模式公开(公告)号：US20050063213A1
公开(公告)日：2005-03-24
申请号：US10665402
申请日：2003-09-18
申请人： Michael Jacob , Thomas Roehr , Hans-Oliver Joachim
发明人： Michael Jacob , Thomas Roehr , Hans-Oliver Joachim
CPC分类号： G11C29/50 , G11C11/22 , G11C2029/5002 , G11C2029/5004
摘要： The present invention provides a semiconductor memory test mode configuration. A first capacitor stores digital data and connects a cell plate line to a first bit-line through a first select transistor. The first select transistor is activated through a connection to a word line. At least one reference capacitor provides a reference voltage to a reference bit-line. A sense amplifier is connected to the first and reference bit-lines and measures a differential read signal on the first and reference bit-lines. A charge path reduces the differential read signal to determine the signal margin of the semiconductor memory.
摘要翻译： 本发明提供半导体存储器测试模式配置。 第一电容器存储数字数据，并且通过第一选择晶体管将单元板线连接到第一位线。 第一个选择晶体管通过与字线的连接来激活。 至少一个参考电容器为参考位线提供参考电压。 读出放大器连接到第一和参考位线，并测量第一和参考位线上的差分读取信号。 充电路径减小差分读取信号以确定半导体存储器的信号余量。
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公开(公告)号：US06999887B2
公开(公告)日：2006-02-14
申请号：US10636369
申请日：2003-08-06
IPC分类号： G06F3/06
CPC分类号： G11C29/50 , G11C11/22 , G11C2029/5004
摘要： A memory cell signal window testing apparatus 101 and method for testing the signal window of a memory are disclosed. First data is written to a memory cell during a write cycle. A low cell signal is read from the memory cell during a first read cycle. A comparison is made between the low signal and a low reference signal. The result of the comparison is stored in a first storage register. Second data is then written to the memory cell during a write cycle. A high cell signal is read from the memory cell during a second read cycle. A comparison is made between the high cell signal and a high reference signal. The result of the comparison is stored in a second storage register. The results in the first and second storage registers are compared and an output is provided indicating that the memory cell has failed the test if the comparison shows that both the low cell signal is higher than the low reference signal and the high cell signal is lower than the high reference signal.
摘要翻译： 公开了一种用于测试存储器的信号窗口的存储单元信号窗口测试装置101和方法。 在写入周期期间，首先将数据写入存储单元。 在第一读取周期期间从存储器单元读取低电平信号。 比较低信号和低参考信号。 比较结果存储在第一存储寄存器中。 在写入周期期间，第二个数据被写入存储单元。 在第二读取周期期间，从存储器单元读取高电平信号。 在高电平信号和高参考信号之间进行比较。 比较结果存储在第二存储寄存器中。 比较第一和第二存储寄存器中的结果，并且提供指示如果比较显示低电平信号低于低参考信号并且高电平信号低于的信号，则存储器单元未通过测试的输出 高参考信号。
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7.发明申请Reference circuit implemented to reduce the degradation of reference capacitors providing reference voltages for 1T1C FeRAM devices 审中-公开实现参考电路，以减少为1T1C FeRAM器件提供参考电压的参考电容的劣化公开(公告)号：US20050063212A1
公开(公告)日：2005-03-24
申请号：US10665401
申请日：2003-09-18
IPC分类号： G11C11/22
CPC分类号： G11C11/22 , G11C2029/5002 , G11C2029/5004
摘要： A semiconductor memory comprises a first capacitor for storing digital data connecting a cell plate line to a first bit-line through a first select transistor. The first select transistor is activated through a connection to a word line. At least one reference capacitor provides a reference voltage to a reference bit-line. A sense amplifier connected to the first and reference bit-lines measures a differential read signal on the first and reference bit-lines. A toggle flip flop alternately changes the polarization of charge stored on the reference capacitors.
摘要翻译： 半导体存储器包括用于存储通过第一选择晶体管将单元板线连接到第一位线的数字数据的第一电容器。 第一个选择晶体管通过与字线的连接来激活。 至少一个参考电容器为参考位线提供参考电压。 连接到第一和参考位线的读出放大器测量第一和参考位线上的差分读取信号。 触发触发器交替地改变存储在参考电容器上的电荷的极化。
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公开(公告)号：US20050033541A1
公开(公告)日：2005-02-10
申请号：US10636369
申请日：2003-08-06
CPC分类号： G11C29/50 , G11C11/22 , G11C2029/5004
摘要： A memory cell signal window testing apparatus 101 and method for testing the signal window of a memory are disclosed. First data is written to a memory cell during a write cycle. A low cell signal is read from the memory cell during a first read cycle. A comparison is made between the low signal and a low reference signal. The result of the comparison is stored in a first storage register. Second data is then written to the memory cell during a write cycle. A high cell signal is read from the memory cell during a second read cycle. A comparison is made between the high cell signal and a high reference signal. The result of the comparison is stored in a second storage register. The results in the first and second storage registers are compared and an output is provided indicating that the memory cell has failed the test if the comparison shows that both the low cell signal is higher than the low reference signal and the high cell signal is lower than the high reference signal.
摘要翻译： 公开了一种用于测试存储器的信号窗口的存储单元信号窗口测试装置101和方法。 在写入周期期间，首先将数据写入存储单元。 在第一读取周期期间从存储器单元读取低电平信号。 比较低信号和低参考信号。 比较结果存储在第一存储寄存器中。 在写入周期期间，第二个数据被写入存储单元。 在第二读取周期期间，从存储器单元读取高电平信号。 在高电平信号和高参考信号之间进行比较。 比较结果存储在第二存储寄存器中。 比较第一和第二存储寄存器中的结果，并且提供指示如果比较显示低电平信号低于低参考信号并且高电平信号低于的信号，则存储器单元未通过测试的输出 高参考信号。
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公开(公告)号：US20050047189A1
公开(公告)日：2005-03-03
申请号：US10651753
申请日：2003-08-29
申请人： Roehr Thomas , Hans-Oliver Joachim , Norbert Rehm
发明人： Roehr Thomas , Hans-Oliver Joachim , Norbert Rehm
IPC分类号： G11C11/22
CPC分类号： G11C11/22
摘要： The present invention includes a ferro fuse cell comprising a ferroelectric storage capacitor electrically connected to a plate on one side and to a sense amplifier on the other side. A ferroelectric measurement capacitor is electrically connected between the ferroelectric storage capacitor and the sense amplifier.
摘要翻译： 本发明包括一个铁熔体单元，其包括电连接到一侧的板和另一侧的读出放大器的铁电存储电容器。 铁电测量电容器电连接在铁电存储电容器和读出放大器之间。
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公开(公告)号：US06584009B1
公开(公告)日：2003-06-24
申请号：US10103360
申请日：2002-03-21
申请人： Thomas Roehr , Hans-Oliver Joachim
发明人： Thomas Roehr , Hans-Oliver Joachim
IPC分类号： G11C1112
摘要： A chained memory IC in which a dual voltage scheme is used for operating the wordlines is described. During standby mode, the wordlines are maintained at a first logic 1 voltage level. To prepare for a memory access, the non-selected wordlines are driven to a boosted voltage while the selected wordline is driven to ground. The first logic 1 voltage level is less than the boosted voltage. This reduces the stress on the gate oxide of the transistors, thus improving reliability of the memory IC.
摘要翻译： 描述了其中使用双电压方案来操作字线的链接存储器IC。 在待机模式期间，字线保持在第一逻辑1电压电平。 为了准备存储器访问，未选择的字线被驱动到升压电压，同时所选择的字线被驱动到地。 第一个逻辑1电压电平小于升压电压。 这降低了晶体管栅极氧化物的应力，从而提高了存储器IC的可靠性。
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