公开(公告)号：US20120087169A1

公开(公告)日：2012-04-12

申请号：US12900232

申请日：2010-10-07

申请人： Harry Kuo ,  Hagop Nazarian

发明人： Harry Kuo ,  Hagop Nazarian

IPC分类号： G11C7/06 ,  G11C11/21 ,  G11C5/06

CPC分类号： G11C13/0004 ,  G11C7/18 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/0028 ,  G11C13/004 ,  G11C13/0061 ,  G11C2207/005 ,  G11C2213/15 ,  G11C2213/78

摘要： A non-volatile memory device includes a plurality of memory units provided in an array, each memory unit having a plurality of resistive memory cells and a local word line. Each resistive memory units has a first end and a second end, the second ends of the resistive memory cells of each memory unit being coupled to the local word line of the corresponding memory unit. A plurality of bit lines is provided, each bit line being coupled to the first end of one of the resistive memory cells. A plurality of select transistors is provided, each select transistor being assigned to one of the memory units and having a drain terminal coupled to the local word line of the assigned memory unit. First and second global word lines are provided, each global word line being coupled to a control terminal of at least one select transistor. First and second source lines are provided, each source line being coupled to a source terminal of at least one select transistor. The memory device is configured to concurrently read out all of the resistive memory cells in one of the memory units selected for a read operation.

摘要翻译： 非易失性存储器件包括设置在阵列中的多个存储器单元，每个存储器单元具有多个电阻存储器单元和本地字线。 每个电阻式存储器单元具有第一端和第二端，每个存储器单元的电阻性存储单元的第二端耦合到相应的存储器单元的本地字线。 提供多个位线，每个位线耦合到一个电阻存储单元的第一端。 提供多个选择晶体管，每个选择晶体管被分配给存储器单元中的一个并且具有耦合到所分配的存储器单元的本地字线的漏极端子。 提供第一和第二全局字线，每个全局字线耦合到至少一个选择晶体管的控制端。 提供第一和第二源极线，每个源极线耦合到至少一个选择晶体管的源极端子。 存储器件被配置为同时读出为读操作选择的存储器单元之一中的所有电阻存储器单元。

公开(公告)号：US07995385B2

公开(公告)日：2011-08-09

申请号：US11929761

申请日：2007-10-30

申请人： Hagop Nazarian ,  Michael Achter ,  Harry Kuo

发明人： Hagop Nazarian ,  Michael Achter ,  Harry Kuo

IPC分类号： G11C16/06

CPC分类号： G11C16/0416 ,  G11C16/0491

摘要： A system comprising a program component that programs one or more non-volatile memory (“NVM”) cells of an array of pairs of NVM cells using FN tunneling, an erase component that erases the one or more NVM cells of the array of pairs of NVM cells using FN tunneling, and a read component that reads the one or more NVM cells of the array of pairs of NVM cells.

摘要翻译： 一种包括程序组件的系统，该程序组件使用FN隧道对一组或多个NVM单元阵列的一个或多个非易失性存储器（“NVM”）单元进行编程，所述擦除组件擦除所述NVM单元阵列的一对或多个NVM单元 使用FN隧道的NVM单元，以及读取组件，其读取NVM单元阵列阵列中的一个或多个NVM单元。

公开(公告)号：US20100284229A1

公开(公告)日：2010-11-11

申请号：US12842409

申请日：2010-07-23

申请人： Chieu Yin CHIA ,  Michael ACHTER ,  Harry KUO ,  Book-Aik ANG

发明人： Chieu Yin CHIA ,  Michael ACHTER ,  Harry KUO ,  Book-Aik ANG

IPC分类号： G11C7/10

CPC分类号： G11C7/12

摘要： A method and structure for passing a bitline voltage regardless of its voltage level via a bitline in a memory device is disclosed. In one embodiment, the method includes detecting the bitline voltage of the bitline, feeding a control signal at an activation voltage level to the bitline pass device to maintain a pass voltage differential of the bitline pass device when the bitline is selected and passing the bitline voltage via the bitline pass device in response to the control signal, where the pass voltage differential is greater than a threshold voltage of the bitline pass device regardless of a level of the bitline voltage.

摘要翻译： 公开了一种通过存储器件中的位线传送位线电压而不管其电压电平的方法和结构。 在一个实施例中，该方法包括检测位线的位线电压，将激活电压电平的控制信号馈送到位线通过器件，以在选择位线并通过位线电压时维持位线通过器件的通过电压差 通过位线传递装置响应于控制信号，其中通过电压差异大于位线通过器件的阈值电压，而与位线电压的电平无关。

公开(公告)号：US20090244989A1

公开(公告)日：2009-10-01

申请号：US12057203

申请日：2008-03-27

申请人： Chieu Yin CHIA ,  Michael ACHTER ,  Harry KUO ,  Boon-Aik ANG

发明人： Chieu Yin CHIA ,  Michael ACHTER ,  Harry KUO ,  Boon-Aik ANG

IPC分类号： G11C7/00

CPC分类号： G11C7/12

摘要： A method and structure for passing a bitline voltage regardless of its voltage level via a bitline in a memory device is disclosed. In one embodiment, the method includes detecting the bitline voltage of the bitline, feeding a control signal at an activation voltage level to the bitline pass device to maintain a pass voltage differential of the bitline pass device when the bitline is selected and passing the bitline voltage via the bitline pass device in response to the control signal, where the pass voltage differential is greater than a threshold voltage of the bitline pass device regardless of a level of the bitline voltage.

摘要翻译： 公开了一种通过存储器件中的位线传送位线电压而不管其电压电平的方法和结构。 在一个实施例中，该方法包括检测位线的位线电压，将激活电压电平的控制信号馈送到位线通过器件，以在选择位线并通过位线电压时维持位线通过器件的通过电压差 通过位线传递装置响应于控制信号，其中通过电压差异大于位线通过器件的阈值电压，而与位线电压的电平无关。

公开(公告)号：US07787313B2

公开(公告)日：2010-08-31

申请号：US12057203

申请日：2008-03-27

申请人： Chieu Yin Chia ,  Michael Achter ,  Harry Kuo ,  Boon-Aik Ang

发明人： Chieu Yin Chia ,  Michael Achter ,  Harry Kuo ,  Boon-Aik Ang

IPC分类号： G11C7/10

CPC分类号： G11C7/12

摘要： A method and structure for passing a bitline voltage regardless of its voltage level via a bitline in a memory device is disclosed. In one embodiment, the method includes detecting the bitline voltage of the bitline, feeding a control signal at an activation voltage level to the bitline pass device to maintain a pass voltage differential of the bitline pass device when the bitline is selected and passing the bitline voltage via the bitline pass device in response to the control signal, where the pass voltage differential is greater than a threshold voltage of the bitline pass device regardless of a level of the bitline voltage.

摘要翻译： 公开了一种通过存储器件中的位线传送位线电压而不管其电压电平的方法和结构。 在一个实施例中，该方法包括检测位线的位线电压，将激活电压电平的控制信号馈送到位线通过器件，以在选择位线并通过位线电压时维持位线通过器件的通过电压差 通过位线传递装置响应于控制信号，其中通过电压差异大于位线通过器件的阈值电压，而与位线电压的电平无关。

公开(公告)号：US20090109758A1

公开(公告)日：2009-04-30

申请号：US11929761

申请日：2007-10-30

申请人： Hagop Nazarian ,  Michael Achter ,  Harry Kuo

发明人： Hagop Nazarian ,  Michael Achter ,  Harry Kuo

IPC分类号： G11C16/04

CPC分类号： G11C16/0416 ,  G11C16/0491

摘要： A system comprising a program component that programs one or more non-volatile memory (“NVM”) cells of an array of pairs of NVM cells using FN tunneling, an erase component that erases the one or more NVM cells of the array of pairs of NVM cells using FN tunneling, and a read component that reads the one or more NVM cells of the array of pairs of NVM cells.

摘要翻译： 一种包括程序组件的系统，该程序组件使用FN隧道对一组或多个NVM单元阵列的一个或多个非易失性存储器（“NVM”）单元进行编程，所述擦除组件擦除所述NVM单元阵列的一对或多个NVM单元 使用FN隧道的NVM单元，以及读取组件，其读取NVM单元阵列阵列中的一个或多个NVM单元。

公开(公告)号：US08315079B2

公开(公告)日：2012-11-20

申请号：US12900232

申请日：2010-10-07

申请人： Harry Kuo ,  Hagop Nazarian

发明人： Harry Kuo ,  Hagop Nazarian

IPC分类号： G11C7/06

CPC分类号： G11C13/0004 ,  G11C7/18 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/0028 ,  G11C13/004 ,  G11C13/0061 ,  G11C2207/005 ,  G11C2213/15 ,  G11C2213/78

摘要： A non-volatile memory device includes an array of memory units, each having resistive memory cells and a local word line. Each memory cell has a first and a second end, the second ends are coupled to the local word line of the corresponding memory unit. Bit lines are provided, each coupled to the first end of each resistive memory cell. A plurality of select transistors is provided, each associated with one memory unit and having a drain terminal coupled to the local word line of the associated memory unit. First and second global word lines are provided, each coupled to a control terminal of at least one select transistor. First and second source lines are provided, each coupled to a source terminal of at least one select transistor. The memory device is configured to concurrently read out all resistive memory cells in one selected memory unit in a read operation.

摘要翻译： 非易失性存储器件包括存储单元阵列，每个存储器单元具有电阻存储器单元和本地字线。 每个存储单元具有第一端和第二端，第二端耦合到相应存储单元的本地字线。 提供位线，每一个都连接到每个电阻存储器单元的第一端。 提供了多个选择晶体管，每个选择晶体管与一个存储器单元相关联并且具有耦合到相关联的存储器单元的本地字线的漏极端子。 提供第一和第二全局字线，每个字线耦合到至少一个选择晶体管的控制端。 提供第一和第二源极线，每个耦合到至少一个选择晶体管的源极端子。 存储器件被配置为在读取操作中同时读出一个选择的存储器单元中的所有电阻存储器单元。

公开(公告)号：US07894267B2

公开(公告)日：2011-02-22

申请号：US11929741

申请日：2007-10-30

申请人： Hagop Nazarian ,  Michael Achter ,  Harry Kuo

发明人： Hagop Nazarian ,  Michael Achter ,  Harry Kuo

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C16/10 ,  G11C16/12

摘要： Systems and methods for improving the programming of memory devices. A pulse component applies different programming pulses to a memory cell. An analysis component measures values of one or more characteristics of the memory cell as a function of the applied different programming pulses. A computation component computes the applied different programming pulses as a function of the measured values of the one or more characteristics of the memory cell. The analysis component measures one or more values of the one or more characteristics of the memory cell, the computation component computes one or more programming pulses as a function of the one or more measured values of the one or more characteristics of the memory cell, and the pulse component applies the one or more programming pulses to the memory cell.

摘要翻译： 改进存储器件编程的系统和方法。 脉冲分量将不同的编程脉冲施加到存储单元。 分析组件根据应用的不同编程脉冲测量存储器单元的一个或多个特性的值。 计算组件根据存储单元的一个或多个特性的测量值来计算应用的不同编程脉冲。 分析组件测量存储器单元的一个或多个特性的一个或多个值，计算组件根据存储器单元的一个或多个特性的一个或多个测量值来计算一个或多个编程脉冲，以及 脉冲分量将一个或多个编程脉冲施加到存储器单元。

公开(公告)号：US08295102B2

公开(公告)日：2012-10-23

申请号：US12842409

申请日：2010-07-23

申请人： Chieu Yin Chia ,  Michael Achter ,  Harry Kuo ,  Book-Aik Ang

发明人： Chieu Yin Chia ,  Michael Achter ,  Harry Kuo ,  Book-Aik Ang

IPC分类号： G11C7/10

CPC分类号： G11C7/12

摘要： A method and structure for passing a bitline voltage regardless of its voltage level via a bitline in a memory device is disclosed. In one embodiment, the method includes detecting the bitline voltage of the bitline, feeding a control signal at an activation voltage level to the bitline pass device to maintain a pass voltage differential of the bitline pass device when the bitline is selected and passing the bitline voltage via the bitline pass device in response to the control signal, where the pass voltage differential is greater than a threshold voltage of the bitline pass device regardless of a level of the bitline voltage.

摘要翻译： 公开了一种通过存储器件中的位线传送位线电压而不管其电压电平的方法和结构。 在一个实施例中，该方法包括检测位线的位线电压，将激活电压电平的控制信号馈送到位线通过器件，以在选择位线并通过位线电压时维持位线通过器件的通过电压差 通过位线传递装置响应于控制信号，其中通过电压差异大于位线通过器件的阈值电压，而与位线电压的电平无关。

公开(公告)号：US20090109760A1

公开(公告)日：2009-04-30

申请号：US11929741

申请日：2007-10-30

申请人： Hagop Nazarian ,  Michael Achter ,  Harry Kuo

发明人： Hagop Nazarian ,  Michael Achter ,  Harry Kuo

IPC分类号： G11C11/34

CPC分类号： G11C16/10 ,  G11C16/12

摘要： Systems and methods for improving the programming of memory devices. A pulse component applies different programming pulses to a memory cell. An analysis component measures values of one or more characteristics of the memory cell as a function of the applied different programming pulses. A computation component computes the applied different programming pulses as a function of the measured values of the one or more characteristics of the memory cell. The analysis component measures one or more values of the one or more characteristics of the memory cell, the computation component computes one or more programming pulses as a function of the one or more measured values of the one or more characteristics of the memory cell, and the pulse component applies the one or more programming pulses to the memory cell.

摘要翻译： 改进存储器件编程的系统和方法。 脉冲分量将不同的编程脉冲施加到存储单元。 分析组件根据应用的不同编程脉冲测量存储器单元的一个或多个特性的值。 计算组件根据存储单元的一个或多个特性的测量值来计算应用的不同编程脉冲。 分析组件测量存储器单元的一个或多个特性的一个或多个值，计算组件根据存储器单元的一个或多个特性的一个或多个测量值来计算一个或多个编程脉冲，以及 脉冲分量将一个或多个编程脉冲施加到存储器单元。