公开(公告)号：US08154088B1

公开(公告)日：2012-04-10

申请号：US11860245

申请日：2007-09-24

申请人： Antoine Khoueir ,  Subhash Srinivas Pidaparthi ,  Henry Jim Fulford

发明人： Antoine Khoueir ,  Subhash Srinivas Pidaparthi ,  Henry Jim Fulford

IPC分类号： H01L27/088 ,  H01L21/338 ,  H01L21/84 ,  H01L21/8238 ,  H01L21/336 ,  H01L21/425

CPC分类号： H01L21/823814 ,  H01L21/823418 ,  H01L21/823481 ,  H01L21/823878 ,  H01L29/6653

摘要： Improved semiconductor topographies and methods are provided herein for reducing the gate induced drain leakage (GIDL) associated with MOS transistors. In particular, a disposable spacer layer is used as an additional mask during implantation of one or more source/drain regions. The physical spacing between the gate and the source/drain regions of a MOS transistor (i.e., the gate/drain overlap) can be varied by varying the thickness of the disposable spacer layer. For example, a larger spacer layer thickness may be used to decrease the gate/drain overlap and reduce the GIDL associated with the MOS transistor. The disposable spacer layer is completely removed after implantation to enable electrical contact between the source/drain regions and subsequently formed source/drain contacts. A method is also provided herein for independently customizing the amount of current leakage associated with two or more MOS transistors.

摘要翻译： 本文提供了改进的半导体拓扑图和方法，用于减少与MOS晶体管相关的栅极感应漏极泄漏（GIDL）。 特别地，在一个或多个源极/漏极区域的注入期间，一次性间隔层被用作附加掩模。 可以通过改变一次性间隔层的厚度来改变MOS晶体管的栅极和源极/漏极区域之间的物理间隔（即，栅极/漏极重叠）。 例如，可以使用更大的间隔层厚度来减小栅极/漏极重叠并且减小与MOS晶体管相关联的GIDL。 一次性间隔层在植入之后被完全去除，以使得源极/漏极区域和随后形成的源极/漏极接触点之间能够电接触。 本文还提供了一种用于独立地定制与两个或多个MOS晶体管相关联的电流泄漏量的方法。

公开(公告)号：US20110140204A1

公开(公告)日：2011-06-16

申请号：US12639158

申请日：2009-12-16

申请人： Michael Smith ,  Vladimir Mikhalev ,  Puneet Sharma ,  Zia Alan Shafi ,  Henry Jim Fulford

发明人： Michael Smith ,  Vladimir Mikhalev ,  Puneet Sharma ,  Zia Alan Shafi ,  Henry Jim Fulford

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7833 ,  H01L21/266 ,  H01L27/105 ,  H01L29/0634 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/423 ,  H01L29/6659

摘要： Methods of forming transistors and transistors are disclosed, such as a transistor having a gate dielectric over a semiconductor having a first conductivity type, a control gate over the gate dielectric, source and drain regions having a second conductivity type in the semiconductor having the first conductivity type, and strips having the second conductivity type within the semiconductor having the first conductivity type and interposed between the control gate and at least one of the source and drain regions.

摘要翻译： 公开了形成晶体管和晶体管的方法，例如在具有第一导电类型的半导体上具有栅极电介质的晶体管，栅极电介质上的控制栅极，具有第一导电性的半导体中的第二导电类型的源极和漏极区域 型和具有第二导电类型的带在具有第一导电类型的半导体内并且插入在控制栅极和源极和漏极区域中的至少一个之间的条带。

公开(公告)号：US08969928B2

公开(公告)日：2015-03-03

申请号：US12872814

申请日：2010-08-31

申请人： Mike Smith ,  Henry Jim Fulford

发明人： Mike Smith ,  Henry Jim Fulford

IPC分类号： H01L29/78 ,  H01L21/265 ,  H01L29/423 ,  H01L29/66 ,  H01L29/06 ,  H01L29/10

CPC分类号： H01L21/26586 ,  H01L29/0607 ,  H01L29/1045 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/66484 ,  H01L29/7833

摘要： Transistors having a dielectric over a semiconductor, a control gate over the dielectric at a particular level, and one or more conductive structures over the dielectric at the particular level facilitate control of device characteristics of the transistor. The one or more conductive structures are between the control gate and at least one source/drain region of the transistor. The one or more conductive structures are electrically isolated from the control gate.

摘要翻译： 具有在半导体上的电介质，在特定电平上的电介质上的控制栅极和在特定水平面上的电介质上的一个或多个导电结构的晶体管便于控制晶体管的器件特性。 一个或多个导电结构位于晶体管的控制栅极和至少一个源极/漏极区域之间。 一个或多个导电结构与控制栅极电隔离。

公开(公告)号：US08815667B2

公开(公告)日：2014-08-26

申请号：US12639158

申请日：2009-12-16

申请人： Michael Smith ,  Vladimir Mikhalev ,  Puneet Sharma ,  Zia Alan Shafi ,  Henry Jim Fulford

发明人： Michael Smith ,  Vladimir Mikhalev ,  Puneet Sharma ,  Zia Alan Shafi ,  Henry Jim Fulford

IPC分类号： H01L21/338

CPC分类号： H01L29/7833 ,  H01L21/266 ,  H01L27/105 ,  H01L29/0634 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/423 ,  H01L29/6659

摘要： Methods of forming transistors and transistors are disclosed, such as a transistor having a gate dielectric over a semiconductor having a first conductivity type, a control gate over the gate dielectric, source and drain regions having a second conductivity type in the semiconductor having the first conductivity type, and strips having the second conductivity type within the semiconductor having the first conductivity type and interposed between the control gate and at least one of the source and drain regions.

摘要翻译： 公开了形成晶体管和晶体管的方法，例如在具有第一导电类型的半导体上具有栅极电介质的晶体管，栅极电介质上的控制栅极，具有第一导电性的半导体中的第二导电类型的源极和漏极区域 型和具有第二导电类型的带在具有第一导电类型的半导体内并且插入在控制栅极和源极和漏极区域中的至少一个之间的条带。

公开(公告)号：US20120049248A1

公开(公告)日：2012-03-01

申请号：US12872814

申请日：2010-08-31

申请人： Mike Smith ,  Henry Jim Fulford

发明人： Mike Smith ,  Henry Jim Fulford

IPC分类号： H01L29/78

CPC分类号： H01L21/26586 ,  H01L29/0607 ,  H01L29/1045 ,  H01L29/42372 ,  H01L29/4238 ,  H01L29/66484 ,  H01L29/7833

摘要： Transistors having a dielectric over a semiconductor, a control gate over the dielectric at a particular level, and one or more conductive structures over the dielectric at the particular level facilitate control of device characteristics of the transistor. The one or more conductive structures are between the control gate and at least one source/drain region of the transistor. The one or more conductive structures are electrically isolated from the control gate.

摘要翻译： 具有在半导体上的电介质，在特定电平上的电介质上的控制栅极和在特定水平面上的电介质上的一个或多个导电结构的晶体管便于控制晶体管的器件特性。 一个或多个导电结构位于晶体管的控制栅极和至少一个源极/漏极区域之间。 一个或多个导电结构与控制栅极电隔离。