公开(公告)号：US20110140204A1

公开(公告)日：2011-06-16

申请号：US12639158

申请日：2009-12-16

申请人： Michael Smith ,  Vladimir Mikhalev ,  Puneet Sharma ,  Zia Alan Shafi ,  Henry Jim Fulford

发明人： Michael Smith ,  Vladimir Mikhalev ,  Puneet Sharma ,  Zia Alan Shafi ,  Henry Jim Fulford

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7833 ,  H01L21/266 ,  H01L27/105 ,  H01L29/0634 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/423 ,  H01L29/6659

摘要： Methods of forming transistors and transistors are disclosed, such as a transistor having a gate dielectric over a semiconductor having a first conductivity type, a control gate over the gate dielectric, source and drain regions having a second conductivity type in the semiconductor having the first conductivity type, and strips having the second conductivity type within the semiconductor having the first conductivity type and interposed between the control gate and at least one of the source and drain regions.

摘要翻译： 公开了形成晶体管和晶体管的方法，例如在具有第一导电类型的半导体上具有栅极电介质的晶体管，栅极电介质上的控制栅极，具有第一导电性的半导体中的第二导电类型的源极和漏极区域 型和具有第二导电类型的带在具有第一导电类型的半导体内并且插入在控制栅极和源极和漏极区域中的至少一个之间的条带。

公开(公告)号：US08815667B2

公开(公告)日：2014-08-26

申请号：US12639158

申请日：2009-12-16

申请人： Michael Smith ,  Vladimir Mikhalev ,  Puneet Sharma ,  Zia Alan Shafi ,  Henry Jim Fulford

发明人： Michael Smith ,  Vladimir Mikhalev ,  Puneet Sharma ,  Zia Alan Shafi ,  Henry Jim Fulford

IPC分类号： H01L21/338

CPC分类号： H01L29/7833 ,  H01L21/266 ,  H01L27/105 ,  H01L29/0634 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/423 ,  H01L29/6659

摘要： Methods of forming transistors and transistors are disclosed, such as a transistor having a gate dielectric over a semiconductor having a first conductivity type, a control gate over the gate dielectric, source and drain regions having a second conductivity type in the semiconductor having the first conductivity type, and strips having the second conductivity type within the semiconductor having the first conductivity type and interposed between the control gate and at least one of the source and drain regions.

摘要翻译： 公开了形成晶体管和晶体管的方法，例如在具有第一导电类型的半导体上具有栅极电介质的晶体管，栅极电介质上的控制栅极，具有第一导电性的半导体中的第二导电类型的源极和漏极区域 型和具有第二导电类型的带在具有第一导电类型的半导体内并且插入在控制栅极和源极和漏极区域中的至少一个之间的条带。

公开(公告)号：US08853833B2

公开(公告)日：2014-10-07

申请号：US13159203

申请日：2011-06-13

申请人： Vladimir Mikhalev ,  Michael Smith ,  Henry J. Fulford ,  Puneet Sharma ,  Zia A. Shafi

发明人： Vladimir Mikhalev ,  Michael Smith ,  Henry J. Fulford ,  Puneet Sharma ,  Zia A. Shafi

IPC分类号： H01L23/552 ,  H01L23/522

CPC分类号： H01L23/552 ,  H01L23/5225 ,  H01L23/5226 ,  H01L23/53271 ,  H01L27/088 ,  H01L29/402 ,  H01L29/404 ,  H01L29/45 ,  H01L29/7833 ,  H01L2924/0002 ,  H03K17/161 ,  H03K17/162 ,  H01L2924/00

摘要： Semiconductor devices are described, along with methods and systems that include them. One such device includes a diffusion region in a semiconductor material, a terminal coupled to the diffusion region, and a field plate coupled to the terminal and extending from the terminal over the diffusion region to shield the diffusion region. Additional embodiments are also described.

摘要翻译： 描述半导体器件以及包括它们的方法和系统。 一种这样的器件包括在半导体材料中的扩散区域，耦合到扩散区域的端子和耦合到端子并且从端子在扩散区域上延伸以屏蔽扩散区域的场板。 还描述了另外的实施例。

公开(公告)号：US20120313691A1

公开(公告)日：2012-12-13

申请号：US13159203

申请日：2011-06-13

申请人： Vladimir Mikhalev ,  Michael Smith ,  Henry J. Fulford ,  Puneet Sharma ,  Zia A. Shafi

发明人： Vladimir Mikhalev ,  Michael Smith ,  Henry J. Fulford ,  Puneet Sharma ,  Zia A. Shafi

IPC分类号： H03K3/01 ,  H01L27/04 ,  H01L23/552

CPC分类号： H01L23/552 ,  H01L23/5225 ,  H01L23/5226 ,  H01L23/53271 ,  H01L27/088 ,  H01L29/402 ,  H01L29/404 ,  H01L29/45 ,  H01L29/7833 ,  H01L2924/0002 ,  H03K17/161 ,  H03K17/162 ,  H01L2924/00

摘要： Semiconductor devices are described, along with methods and systems that include them. One such device includes a diffusion region in a semiconductor material, a terminal coupled to the diffusion region, and a field plate coupled to the terminal and extending from the terminal over the diffusion region to shield the diffusion region. Additional embodiments are also described.

摘要翻译： 描述半导体器件以及包括它们的方法和系统。 一种这样的器件包括在半导体材料中的扩散区域，耦合到扩散区域的端子和耦合到端子并且从端子在扩散区域上延伸以屏蔽扩散区域的场板。 还描述了另外的实施例。

公开(公告)号：US08243526B2

公开(公告)日：2012-08-14

申请号：US12653437

申请日：2009-12-14

申请人： Michael Smith ,  Vladimir Mikhalev ,  Kenneth Marr ,  Haitao Liu

发明人： Michael Smith ,  Vladimir Mikhalev ,  Kenneth Marr ,  Haitao Liu

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： H01L27/11526 ,  H01L27/0266 ,  H01L27/11529

摘要： A non-volatile microelectronic memory device that includes a depletion mode circuit protection device that prevents high voltages, which are applied to bitlines during an erase operation, from being applied to and damaging low voltage circuits which are electrically coupled to the bitlines.

摘要翻译： 一种非易失性微电子存储器件，其包括耗尽模式电路保护装置，其防止在擦除操作期间施加到位线的高电压被施加到和电连接到位线的低电压电路。

公开(公告)号：US20050035799A1

公开(公告)日：2005-02-17

申请号：US10944136

申请日：2004-09-16

申请人： Vladimir Mikhalev ,  Aaron Schoenfeld ,  Daniel Penney ,  William Waldrop

发明人： Vladimir Mikhalev ,  Aaron Schoenfeld ,  Daniel Penney ,  William Waldrop

IPC分类号： G11C7/10 ,  H03L7/081 ,  H03L7/06

CPC分类号： G11C7/1057 ,  G11C7/1051 ,  G11C7/1066 ,  H03L7/0812

摘要： A delay-locked loop adjusts a delay of a clock signal that is generated in response to an external clock signal. The clock signal is applied to an output buffer to clock the buffer so that data or clock signals from the buffer are synchronized with the external clock signal. The output buffer operates in a full-drive and reduced-drive mode in response to an output drive strength bit having first and second logic states, respectively. The delay-locked loop adjusts the delay of the clock signal in response to the state of the output drive strength bit to keep the data or clock signals from the buffer synchronized during both modes of operation.

摘要翻译： 延迟锁定环路调整响应于外部时钟信号而产生的时钟信号的延迟。 时钟信号被施加到输出缓冲器以对缓冲器进行时钟，使得来自缓冲器的数据或时钟信号与外部时钟信号同步。 响应于分别具有第一和第二逻辑状态的输出驱动强度位，输出缓冲器以全驱动和降低驱动模式工作。 延迟锁定环路响应于输出驱动强度位的状态来调整时钟信号的延迟，以在两种操作模式期间保持来自缓冲器的数据或时钟信号同步。

公开(公告)号：US06693472B2

公开(公告)日：2004-02-17

申请号：US10243279

申请日：2002-09-12

申请人： Vladimir Mikhalev ,  Aaron M. Schoenfeld ,  Daniel B. Penney ,  William C. Waldrop

发明人： Vladimir Mikhalev ,  Aaron M. Schoenfeld ,  Daniel B. Penney ,  William C. Waldrop

IPC分类号： H03L706

CPC分类号： G11C7/1057 ,  G11C7/1051 ,  G11C7/1066 ,  H03L7/0812

摘要： A delay-locked loop adjusts a delay of a clock signal that is generated in response to an external clock signal. The clock signal is applied to an output buffer to clock the buffer so that data or clock signals from the buffer are synchronized with the external clock signal. The output buffer operates in a full-drive and reduced-drive mode in response to an output drive strength bit having first and second logic states, respectively. The delay-locked loop adjusts the delay of the clock signal in response to the state of the output drive strength bit to keep the data or clock signals from the buffer synchronized during both modes of operation.

摘要翻译： 延迟锁定环路调整响应于外部时钟信号而产生的时钟信号的延迟。 时钟信号被施加到输出缓冲器以对缓冲器进行时钟，使得来自缓冲器的数据或时钟信号与外部时钟信号同步。 响应于分别具有第一和第二逻辑状态的输出驱动强度位，输出缓冲器以全驱动和降低驱动模式工作。 延迟锁定环路响应于输出驱动强度位的状态来调整时钟信号的延迟，以在两种操作模式期间保持来自缓冲器的数据或时钟信号同步。

公开(公告)号：US20120329231A1

公开(公告)日：2012-12-27

申请号：US13603100

申请日：2012-09-04

申请人： Vladimir Mikhalev ,  Jim Fulford ,  Yongjun Jeff Hu ,  Gordon A. Haller ,  Lequn Liu

发明人： Vladimir Mikhalev ,  Jim Fulford ,  Yongjun Jeff Hu ,  Gordon A. Haller ,  Lequn Liu

IPC分类号： H01L21/762 ,  H01L21/336

CPC分类号： H01L21/823462 ,  H01L21/02107 ,  H01L21/02164 ,  H01L21/02282 ,  H01L21/265 ,  H01L21/76224 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/823425 ,  H01L21/823481 ,  H01L29/66575 ,  H01L29/78 ,  H01L29/7846

摘要： Some embodiments include methods of forming isolation structures. A semiconductor base may be provided to have a crystalline semiconductor material projection between a pair of openings. SOD material (such as, for example, polysilazane) may be flowed within said openings to fill the openings. After the openings are filled with the SOD material, one or more dopant species may be implanted into the projection to amorphize the crystalline semiconductor material within an upper portion of said projection. The SOD material may then be annealed at a temperature of at least about 400° C. to form isolation structures. Some embodiments include semiconductor constructions that include a semiconductor material base having a projection between a pair of openings. The projection may have an upper region over a lower region, with the upper region being at least 75% amorphous, and with the lower region being entirely crystalline.

摘要翻译： 一些实施方案包括形成隔离结构的方法。 可以提供半导体基底以在一对开口之间具有晶体半导体材料突起。 SOD材料（例如，聚硅氮烷）可以在所述开口内流动以填充开口。 在用SOD材料填充开口之后，可以将一种或多种掺杂剂物质注入到投影中，使晶体半导体材料在所述突起的上部非晶化。 然后可以在至少约400℃的温度下对SOD材料进行退火以形成隔离结构。 一些实施例包括半导体结构，其包括在一对开口之间具有突起的半导体材料基底。 突起可以在下部区域上方具有上部区域，其中上部区域为至少75％的无定形，并且下部区域是完全结晶的。

公开(公告)号：US07272742B2

公开(公告)日：2007-09-18

申请号：US10931358

申请日：2004-08-31

申请人： Aaron M. Schoenfeld ,  Vladimir Mikhalev

发明人： Aaron M. Schoenfeld ,  Vladimir Mikhalev

IPC分类号： G06F1/04

CPC分类号： G06F1/10 ,  G06F1/12 ,  G06F13/4217

摘要： A method and apparatus for improving output skew across the data bus of a synchronous integrated circuit device. The device includes a clock input buffer that receives a system clock signal and generates a buffered clock signal, a delay line that receives the buffered clock signal and generates a delayed clock signal, and an output circuit including output signal paths for outputting the output signals synchronously with the system clock signal by using the delayed clock signal. At least one of the output signal paths includes a delay circuit and an output buffer. Each delay circuit provides a programmable delay to the delayed clock signal to generate a unique delayed clock signal used to clock an output signal into the respective output buffer. By programming the delays based upon output skew, the output skew can be improved.

摘要翻译： 一种用于改善跨同步集成电路器件的数据总线的输出偏移的方法和装置。 该装置包括时钟输入缓冲器，其接收系统时钟信号并产生缓冲的时钟信号，延迟线，其接收经缓冲的时钟信号并产生延迟的时钟信号;以及输出电路，包括用于同步输出输出信号的输出信号路径 通过使用延迟的时钟信号与系统时钟信号。 输出信号路径中的至少一个包括延迟电路和输出缓冲器。 每个延迟电路为延迟的时钟信号提供可编程延迟，以产生用于将输出信号时钟输入到相应输出缓冲器中的唯一的延迟时钟信号。 通过基于输出偏移来编程延迟，可以提高输出偏移。

公开(公告)号：US06975149B2

公开(公告)日：2005-12-13

申请号：US10944136

申请日：2004-09-16

申请人： Vladimir Mikhalev ,  Aaron M. Schoenfeld ,  Daniel B. Penney ,  William C. Waldrop

发明人： Vladimir Mikhalev ,  Aaron M. Schoenfeld ,  Daniel B. Penney ,  William C. Waldrop

IPC分类号： G11C7/10 ,  H03L7/081 ,  H03L7/06

CPC分类号： G11C7/1057 ,  G11C7/1051 ,  G11C7/1066 ,  H03L7/0812

摘要： A delay-locked loop adjusts a delay of a clock signal that is generated in response to an external clock signal. The clock signal is applied to an output buffer to clock the buffer so that data or clock signals from the buffer are synchronized with the external clock signal. The output buffer operates in a full-drive and reduced-drive mode in response to an output drive strength bit having first and second logic states, respectively. The delay-locked loop adjusts the delay of the clock signal in response to the state of the output drive strength bit to keep the data or clock signals from the buffer synchronized during both modes of operation.