Polarity driven dynamic on-die termination
    1.
    发明授权
    Polarity driven dynamic on-die termination 有权
    极性驱动动态片上终端

    公开(公告)号:US07372293B2

    公开(公告)日:2008-05-13

    申请号:US11296950

    申请日:2005-12-07

    IPC分类号: H03K17/16 H03K19/003

    摘要: Embodiments of the invention are generally directed to systems, methods, and apparatuses for polarity driven on-die termination. In some embodiments, an integrated circuit includes an input/output (I/O) circuit to receive a command and an on-die termination (ODT) pin to receive one or more ODT signals. The integrated circuit may further include control logic coupled to the ODT pin, the control logic to enable, at least in part, a multiplexing of an ODT activation signal and an ODT value selection signal on the ODT pin, the control logic further to control a length of termination based, at least in part, on the command. Other embodiments are described and claimed.

    摘要翻译: 本发明的实施例一般涉及用于极性驱动的片上端接的系统,方法和装置。 在一些实施例中,集成电路包括用于接收命令的输入/输出(I / O)电路和用于接收一个或多个ODT信号的片上终端(ODT)引脚。 集成电路还可以包括耦合到ODT引脚的控制逻辑,所述控制逻辑至少部分地使得ODT引脚上的ODT激活信号和ODT值选择信号的复用,所述控制逻辑进一步控制 至少部分地基于命令的长度。 描述和要求保护其他实施例。

    Polarity driven dynamic on-die termination
    2.
    发明申请
    Polarity driven dynamic on-die termination 有权
    极性驱动动态片上终端

    公开(公告)号:US20070126463A1

    公开(公告)日:2007-06-07

    申请号:US11296950

    申请日:2005-12-07

    IPC分类号: H03K19/003

    摘要: Embodiments of the invention are generally directed to systems, methods, and apparatuses for polarity driven on-die termination. In some embodiments, an integrated circuit includes an input/output (I/O) circuit to receive a command and an on-die termination (ODT) pin to receive one or more ODT signals. The integrated circuit may further include control logic coupled to the ODT pin, the control logic to enable, at least in part, a multiplexing of an ODT activation signal and an ODT value selection signal on the ODT pin, the control logic further to control a length of termination based, at least in part, on the command. Other embodiments are described and claimed.

    摘要翻译: 本发明的实施例一般涉及用于极性驱动的片上端接的系统,方法和装置。 在一些实施例中,集成电路包括用于接收命令的输入/输出(I / O)电路和用于接收一个或多个ODT信号的片上终端(ODT)引脚。 集成电路还可以包括耦合到ODT引脚的控制逻辑,所述控制逻辑至少部分地使得ODT引脚上的ODT激活信号和ODT值选择信号的复用,所述控制逻辑进一步控制 至少部分地基于命令的长度。 描述和要求保护其他实施例。

    Per byte lane dynamic on-die termination
    3.
    发明申请
    Per byte lane dynamic on-die termination 审中-公开
    每字节通道动态片上端接

    公开(公告)号:US20080197877A1

    公开(公告)日:2008-08-21

    申请号:US11708148

    申请日:2007-02-16

    IPC分类号: H03K19/173

    摘要: Embodiments of the invention are generally directed to systems, methods, and apparatuses for per byte lane dynamic on-die termination. In some embodiments, an integrated circuit includes logic to independently program at least one on-die termination (ODT) value for each of a plurality of integrated circuits coupled together through an interconnect. Other embodiments are described and claimed.

    摘要翻译: 本发明的实施例一般涉及用于每字节通道动态片上终端的系统,方法和装置。 在一些实施例中,集成电路包括用于独立地编程通过互连耦合在一起的多个集成电路中的每一个的至少一个片上终端(ODT)值的逻辑。 描述和要求保护其他实施例。

    Memory system with dynamic termination
    4.
    发明申请
    Memory system with dynamic termination 审中-公开
    内存系统动态终止

    公开(公告)号:US20070247185A1

    公开(公告)日:2007-10-25

    申请号:US11396277

    申请日:2006-03-30

    IPC分类号: H03K19/003

    CPC分类号: H04L25/0298 H04L25/0278

    摘要: The termination impedance of a memory agent may be selected dynamically. A transmission line may be simultaneously terminated with a first impedance at first memory agent and a different impedance at a second memory agent. A memory agent may have a terminator with at least two termination values and logic to dynamically select the termination values. Other embodiments are described and claimed.

    摘要翻译: 可以动态地选择存储器的终止阻抗。 传输线可以以第一存储器处的第一阻抗和第二存储器处的不同阻抗同时终止。 存储器可以具有终止器,其具有至少两个终止值和逻辑以动态地选择终止值。 描述和要求保护其他实施例。