公开(公告)号：US20180247678A1

公开(公告)日：2018-08-30

申请号：US15718388

申请日：2017-09-28

Applicant: George Vergis ,  Dat Le

Inventor： George Vergis ,  Dat Le

IPC: G11C5/14

CPC classification number: G11C5/147 ,  G11C5/04 ,  G11C5/063 ,  G11C5/14 ,  G11C7/1063 ,  G11C2207/10 ,  G11C2207/105

Abstract: In one embodiment, an apparatus comprises a first connector to couple to a connector of a memory card, the memory card comprising a first sense node to sense a supply voltage at a first location of the memory card, the first connector comprising a voltage supply pin; a ground pin; and a sense pin to couple to the first sense node; a first sense line to couple to the first sense node through the sense pin; and a voltage regulator coupled to the first sense line, the voltage regulator to provide the supply voltage based on feedback received from the first sense node of the memory card via the first sense line.

公开(公告)号：US09442871B2

公开(公告)日：2016-09-13

申请号：US13995477

申请日：2011-12-22

Applicant: Kuljit S. Bains ,  Klaus J. Ruff ,  George Vergis ,  Suneeta Sah

Inventor： Kuljit S. Bains ,  Klaus J. Ruff ,  George Vergis ,  Suneeta Sah

IPC: G06F13/28 ,  G06F11/10 ,  G06F11/16 ,  G11C29/44 ,  G06F13/16

CPC classification number: G11C7/1072 ,  G06F11/073 ,  G06F11/0787 ,  G06F11/10 ,  G06F11/1004 ,  G06F11/1016 ,  G06F11/1612 ,  G06F13/16 ,  G06F13/28 ,  G11C7/1006 ,  G11C29/44 ,  G11C2029/0411 ,  G11C2029/4402

Abstract: A register not connected to a data bus is read by transferring data across an address bus to a device connected to the data bus, from which the data is read by a device connected to the data bus. The register resides in a register device connected via the address bus to a memory device that is connected to both the address bus and the data bus. A host processor triggers the register device to transfer information over the address bus to a register on the memory device. The host processor then reads the information from the register of the memory device.

Abstract translation: 通过将地址总线上的数据传送到连接到数据总线的设备，可以读取未连接到数据总线的寄存器，数据由连接到数据总线的设备读取。 寄存器位于通过地址总线连接到连接到地址总线和数据总线两者的存储器件的寄存器中。 主处理器触发寄存器设备通过地址总线将信息传送到存储器设备上的寄存器。 然后主机处理器从存储器件的寄存器读取信息。

公开(公告)号：US20160183374A1

公开(公告)日：2016-06-23

申请号：US14575775

申请日：2014-12-18

Applicant: Mani Prakash ,  Thomas T. Holden ,  Jeffory L. Smalley ,  Ram S. Viswanath ,  Bassam N. Coury ,  Dimitrios Ziakas ,  Chong J. Zhao ,  Jonathan W. Thibado ,  Gregorio R. Murtagian ,  Kuang C. Liu ,  Rajasekaran Swaminathan ,  Zhichao Zhang ,  John M. Lynch ,  David J. Llapitan ,  Sanka Ganesan ,  Xiang Li ,  George Vergis

Inventor： Mani Prakash ,  Thomas T. Holden ,  Jeffory L. Smalley ,  Ram S. Viswanath ,  Bassam N. Coury ,  Dimitrios Ziakas ,  Chong J. Zhao ,  Jonathan W. Thibado ,  Gregorio R. Murtagian ,  Kuang C. Liu ,  Rajasekaran Swaminathan ,  Zhichao Zhang ,  John M. Lynch ,  David J. Llapitan ,  Sanka Ganesan ,  Xiang Li ,  George Vergis

IPC: H05K1/18 ,  H01R12/72 ,  H05K1/11 ,  H05K1/02 ,  H05K3/30 ,  H05K3/34

CPC classification number: H05K1/181 ,  H01L23/00 ,  H01L23/498 ,  H01L2224/16225 ,  H01L2924/15311 ,  H01R12/712 ,  H01R12/79 ,  H05K2201/10159 ,  H05K2201/10325 ,  Y02P70/611

Abstract: Configurable central processing unit (CPU) package substrates are disclosed. A package substrate is described that includes a processing device interface. The package substrate also includes a memory device electrical interface disposed on the package substrate. The package substrate also includes a removable memory mechanical interface disposed proximately to the memory device electrical interface. The removable memory mechanical interface is to allow a memory device to be easily removed from the package substrate after attachment of the memory device to the package substrate.

Abstract translation: 公开了可配置的中央处理单元（CPU）封装基板。 描述了包括处理设备接口的封装衬底。 封装衬底还包括设置在封装衬底上的存储器件电接口。 封装衬底还包括靠近存储器件电接口设置的可移除存储器机械接口。 可移除存储器机械接口是允许在将存储器件附接到封装衬底之后容易地从封装衬底移除存储器件。

公开(公告)号：US20110102230A1

公开(公告)日：2011-05-05

申请号：US13005017

申请日：2011-01-12

Applicant: George Vergis ,  Sunilkumar Mankame

Inventor： George Vergis ,  Sunilkumar Mankame

IPC: H04L17/02

CPC classification number: H04N5/4403 ,  G08C17/02 ,  G08C19/28 ,  G08C19/36 ,  G08C2201/20 ,  H04N21/42225

Abstract: A codeset having function-code combinations is provisioned on a controlling device to control functions of an intended target device. Input is provided to the controlling device which designates a function to be controlled on the intended target device. From a plurality of codes that are each associated with the designated function in a database stored in a memory of the controlling device a first code that is determined to be valid for use in controlling the designated function on the intended target device is selected. When the codeset is then provisioned on the controlling device, the provisioned codeset includes as a function-code combination thereof the designated function and the first code.

Abstract translation: 具有功能代码组合的代码集被提供在控制设备上以控制预期目标设备的功能。 向控制装置提供输入，该控制装置指定要在目标装置上控制的功能。 从存储在控制装置的存储器中的数据库中的与指定功能相关联的多个代码中选择被确定为有效用于控制预期目标设备上的指定功能的第一代码。 当代码集然后在控制设备上被提供时，所提供的代码集包括作为其指定功能和第一代码的功能代码组合。

公开(公告)号：US07414426B2

公开(公告)日：2008-08-19

申请号：US11296993

申请日：2005-12-07

Applicant: Christopher Cox ,  George Vergis

Inventor： Christopher Cox ,  George Vergis

IPC: H03K17/16 ,  H03K19/003

CPC classification number: H04L25/0298 ,  G06F13/4086

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for time-multiplexed dynamic on-die termination. In an embodiment, an integrated circuit receives, during a first clock, an on-die termination (ODT) activation signal at its ODT pin. The integrated circuit also receives, during a second clock, an ODT value selection signal on its ODT pin. In an embodiment, the integrated circuit prevents a reset of the state of the ODT activation signal for a predetermined period of time to enable the multiplexing of signals on the ODT pin. Other embodiments are described and claimed.

Abstract translation: 本发明的实施例一般涉及用于时分复用动态片上终端的系统，方法和装置。 在一个实施例中，集成电路在第一时钟期间接收其ODT引脚上的管芯端接（ODT）激活信号。 在第二个时钟期间，集成电路还在其ODT引脚上接收ODT值选择信号。 在一个实施例中，集成电路防止了ODT激活信号的状态的复位达预定的时间段，以便能够复用ODT引脚上的信号。 描述和要求保护其他实施例。

公开(公告)号：US20070126464A1

公开(公告)日：2007-06-07

申请号：US11296960

申请日：2005-12-07

Applicant: George Vergis ,  Christopher Cox

Inventor： George Vergis ,  Christopher Cox

IPC: H03K19/003

CPC classification number: G11C29/02 ,  G11C5/063 ,  G11C7/1048 ,  G11C7/20 ,  G11C29/025 ,  G11C29/028 ,  G11C29/50008 ,  H04L25/0298

Abstract: Embodiments of the invention are generally directed to systems, methods, and apparatuses for dynamic on-die termination launch latency reduction. In some embodiments, an integrated circuit includes an input/output (I/O) circuit to receive a command and a termination resistance circuit to provide a termination resistance for the I/O circuit. The integrated circuit may further include control logic to establish an initial termination resistance during a preamble associated with the command. Other embodiments are described and claimed.

Abstract translation: 本发明的实施例通常涉及用于动态片上终端启动延迟降低的系统，方法和装置。 在一些实施例中，集成电路包括用于接收命令的输入/输出（I / O）电路和用于为I / O电路提供终端电阻的终端电阻电路。 集成电路还可以包括控制逻辑，以在与命令相关联的前导码段期间建立初始终止电阻。 描述和要求保护其他实施例。

公开(公告)号：US07099735B2

公开(公告)日：2006-08-29

申请号：US10882546

申请日：2004-06-30

Applicant: Sandeep K. Jain ,  George Vergis ,  Animesh Mishra ,  Jun Shi

Inventor： Sandeep K. Jain ,  George Vergis ,  Animesh Mishra ,  Jun Shi

IPC: G01K1/00 ,  G01K1/08 ,  G06F7/00

CPC classification number: G01K7/42

Abstract: In one embodiment a memory controller is provided. The memory controller comprises a predictive logic circuit to predict an increase in a current operating temperature of a memory device coupled to the memory controller, based on memory cycles to be issued to the memory device; and a temperature control circuit to perform a temperature control operation wherein if the sum of the current operating temperature and the predicted increase in temperature is greater than a threshold temperature associated with the memory device, then the number of memory cycles issued to the memory device is reduced.

公开(公告)号：US20140192607A1

公开(公告)日：2014-07-10

申请号：US13976791

申请日：2012-05-08

Applicant: Kuljit Bains ,  George Vergis

Inventor： Kuljit Bains ,  George Vergis

IPC: G11C5/14

CPC classification number: G11C5/145 ,  G11C11/4074 ,  G11C29/021 ,  G11C29/028

Abstract: A memory subsystem includes an adaptive output voltage to provide a voltage based on a power profile of a memory device of the memory subsystem. A charge pump increases the voltage to a level needed to write data to the memory device. The voltage provided is based on the power profile of the memory device, which indicates a voltage level that provides good efficiency for the charge pump, and is within maximum levels for the memory device. The voltage can be higher than a nominal voltage indicated for the memory device in a specification.

Abstract translation: 存储器子系统包括自适应输出电压，以基于存储器子系统的存储器件的功率曲线来提供电压。 电荷泵将电压提高到将数据写入存储器件所需的水平。 所提供的电压基于存储器件的功率曲线，其指示为电荷泵提供良好效率的电压电平，并且在存储器件的最大电平内。 电压可以高于规范中为存储器件指示的额定电压。

公开(公告)号：US20140013168A1

公开(公告)日：2014-01-09

申请号：US13997850

申请日：2012-03-31

Applicant: Kuljit Singh Bains ,  George Vergis

Inventor： Kuljit Singh Bains ,  George Vergis

IPC: G06F11/10

CPC classification number: G06F11/10 ,  G06F11/108 ,  G11C5/04 ,  G11C7/1063 ,  G11C29/42 ,  G11C29/44 ,  G11C2029/0409 ,  G11C2029/0411

Abstract: A memory subsystem has multiple memory devices coupled to a command/address line and an error alert line, the error alert line delay-compensated to provide deterministic alert signal timing. The command/address line and the error alert line are connected between the memory devices and a memory controller that manages the memory devices. The command/address line is driven by the memory controller, and the error alert line is driven by the memory devices.

Abstract translation: 存储器子系统具有耦合到命令/地址线和错误警报线的多个存储器件，误差警报线被延迟补偿以提供确定性警报信号定时。 命令/地址线和错误警报线连接在存储器件和管理存储器件的存储器控​​制器之间。 命令/地址线由存储器控制器驱动，错误警报线由存储器件驱动。

公开(公告)号：US20110252193A1

公开(公告)日：2011-10-13

申请号：US12758667

申请日：2010-04-12

Applicant: Kuljit S. Bains ,  George Vergis

Inventor： Kuljit S. Bains ,  George Vergis

IPC: G06F12/00

CPC classification number: G11C11/406 ,  G11C11/40611

Abstract: A system, device, and method for designating a first rank among a plurality of memory ranks of a Memory Module as a primary rank and a second one or more ranks as secondary ranks, triggering, via hardware logic internal to the Memory Module coupled with the plurality of memory ranks, a refresh of the primary rank at a first time (e.g., Time1), and triggering a non overlapping staggered refresh of each of the secondary ranks at a second one or more times (e.g., Time2 through Timen) corresponding to each of the respective memory ranks designated as the secondary ranks.

Abstract translation: 一种用于将作为主等级的存储器模块的多个存储器级别中的第一级指定为第二级别的第二级别的系统，设备和方法，并且经由与存储器模块耦合的存储器模块内部的硬件逻辑触发， 多个存储器等级，第一次刷新主等级（例如，Time1），并且在第二次或更多次（例如，Time2至Timen）触发每个次级队列的非重叠交错刷新，对应于 每个相应的记忆级别被指定为次级排名。