公开(公告)号：US20120273653A1

公开(公告)日：2012-11-01

申请号：US13210615

申请日：2011-08-16

申请人： Jaroslav HYNECEK ,  Hirofumi Komori ,  Xia Zhao

发明人： Jaroslav HYNECEK ,  Hirofumi Komori ,  Xia Zhao

IPC分类号： H01L27/148 ,  G01J1/42 ,  H01L27/146 ,  H01L31/18

CPC分类号： H01L27/14679 ,  G01J1/4228 ,  G01J1/44 ,  H01L27/1464

摘要： The present invention relates to a junction gate photo-diode (JGP) pixel that includes a JGP for accumulating charge in response to impinging photons. The JGP is positioned on a substrate and includes a top n layer, a middle p layer and a bottom n layer forming a n-p-n junction, and a control terminal coupled to the top n layer. Also included is a floating diffusion (FD) positioned on the substrate and coupled to a pixel output line through an amplifier. Also included is a pinned barrier (PB) positioned on the substrate between the JGP and the FD, the PB temporarily blocks charge transfer between the JGP and the FD. The accumulated charge is transferred from the JGP to FD by applying a control voltage to the JGP control terminal.

摘要翻译： 本发明涉及一种结栅光电二极管（JGP）像素，其包括用于响应入射光子累积电荷的JGP。 JGP位于衬底上，并且包括形成n-p-n结的顶部n层，中间p层和底部n层，以及耦合到顶部n层的控制端子。 还包括位于衬底上并通过放大器耦合到像素输出线的浮动扩散（FD）。 还包括位于JGP和FD之间的衬底上的钉扎屏障（PB），PB暂时阻止JGP和FD之间的电荷转移。 通过向JGP控制端子施加控制电压，将累积电荷从JGP传送到FD。

公开(公告)号：US07936228B2

公开(公告)日：2011-05-03

申请号：US12096528

申请日：2006-12-05

申请人： Hirofumi Komori ,  Takeshi Sagara

发明人： Hirofumi Komori ,  Takeshi Sagara

IPC分类号： H04H20/48 ,  H03C3/00

CPC分类号： H03C3/095 ,  H04H20/48

摘要： An input signal is input via a first resistor to an inverting input terminal of an operational amplifier. A second resistor is provided on a feedback path between an output terminal and the inverting input terminal of the operational amplifier. A control voltage Vcnt output from the operational amplifier is input to a VCO. A frequency divider frequency-divides an output signal Sout of the VCO. A phase comparator compares an output signal from the frequency divider with a reference clock signal and outputs a voltage according to a phase difference. A loop filter removes a high-frequency component of an output voltage Vcp of the phase comparator and outputs the voltage to a non-inverting input terminal of the operational amplifier.

摘要翻译： 输入信号通过第一电阻输入到运算放大器的反相输入端。 第二电阻器设置在运算放大器的输出端子和反相输入端子之间的反馈路径上。 从运算放大器输出的控制电压Vcnt被输入到VCO。 分频器对VCO的输出信号Sout进行分频。 相位比较器将来自分频器的输出信号与参考时钟信号进行比较，并根据相位差输出电压。 环路滤波器去除相位比较器的输出电压Vcp的高频分量，并将该电压输出到运算放大器的非反相输入端。

公开(公告)号：US07230289B2

公开(公告)日：2007-06-12

申请号：US10849238

申请日：2004-05-20

申请人： Hirofumi Komori

发明人： Hirofumi Komori

IPC分类号： H01L31/062 ,  H01L21/113

CPC分类号： H01L27/14689 ,  H01L27/14603 ,  H01L27/1461 ,  H01L27/14612 ,  H01L27/14623

摘要： The MOS type solid-state imaging device has plural pixels each of which comprises a photo-diode and a MOS transistor on a substrate. A gate electrode is formed on the channel dope layer formed in the surface of the p-type well layer. By ion implantation of n-type impurity ions via the gate electrode as the mask, the n-type source region and the drain region are formed in the region corresponding to the MOS transistor, and the n-type impurity region is also formed in the region corresponding to the photo-diode. In the well layer, a high impurity density region as a hole pocket is self-aligned to the gate electrode.

摘要翻译： MOS型固态成像器件具有多个像素，每个像素在衬底上包括光电二极管和MOS晶体管。 在p型阱层的表面形成的沟道掺杂层上形成栅电极。 通过栅极电极作为掩模离子注入n型杂质离子，在与MOS晶体管相对应的区域中形成n型源极区域和漏极区域，并且n型杂质区域也形成在 区域对应于光电二极管。 在阱层中，作为空穴的高杂质浓度区域与栅电极自对准。

公开(公告)号：US06847080B2

公开(公告)日：2005-01-25

申请号：US10324294

申请日：2002-12-19

申请人： Hirofumi Komori ,  Mitsuru Yoshikawa

发明人： Hirofumi Komori ,  Mitsuru Yoshikawa

IPC分类号： H01L21/8234 ,  H01L21/00 ,  H01L21/311 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/01 ,  H01L27/088 ,  H01L27/092

CPC分类号： H01L21/823418 ,  H01L21/26586 ,  H01L21/823468 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： The objective of this invention is to provide a semiconductor device and its manufacturing method with which the offset can be kept fixed even in high breakdown voltage MOS transistors, and that can accommodate high voltages for high breakdown voltage MOS transistors and miniaturization of MOS transistors for low voltage drive. Its constitution provides for inner side wall insulating films 14 and 24 and outer side wall insulating films 16 and 26 formed at both sides of the gate electrodes 12 and 22 in both high breakdown voltage transistor TR2 and transistor TR1 for low voltage drive, and heavily doped region 27 is formed in breakdown voltage transistor TR2 using both inner side wall insulating film 24 and outer side wall insulating film 26 as masks so that offset d2 is controlled by the combined widths of the two side wall insulating films. In transistor TR1 for low voltage drive, heavily doped region 15 is formed using only inner side wall insulating film 14 as the mask, and offset d1 is controlled.

摘要翻译： 本发明的目的是提供一种半导体器件及其制造方法，即使在高击穿电压MOS晶体管中也可以保持偏移，并且可以适应高击穿电压MOS晶体管的高电压和低MOS晶体管的小型化 电压驱动。 其结构提供了用于低电压驱动的高耐压晶体管TR2和晶体管TR1中形成在栅电极12和22两侧的内侧壁绝缘膜14和24以及外侧壁绝缘膜16和26，以及重掺杂 使用内侧壁绝缘膜24和外侧壁绝缘膜26作为掩模，在击穿电压晶体管TR2中形成区域27，使得偏移d2由两个侧壁绝缘膜的组合宽度控制。 在用于低电压驱动的晶体管TR1中，仅使用内侧壁绝缘膜14作为掩模形成重掺杂区域15，并且控制偏移量d1。

公开(公告)号：US5453632A

公开(公告)日：1995-09-26

申请号：US220087

申请日：1994-03-30

申请人： Jaroslav Hynecek ,  Hiroaki Shibuya ,  Hirofumi Komori

发明人： Jaroslav Hynecek ,  Hiroaki Shibuya ,  Hirofumi Komori

IPC分类号： H01L27/148 ,  H01L29/78

CPC分类号： H01L27/14887

摘要： The lateral overflow drain for virtual phase devices includes: a semiconductor region 72 of a first conductivity type; a drain region 24 of the first conductivity type formed in the semiconductor region 72; a threshold adjust region 22 formed in the semiconductor region 72 and surrounding the drain region 24; an electrode 20 overlying and connected to the drain region 24, the electrode 20 overlying and separated from at least a portion of the threshold adjust region 22; and virtual gates 30 and 32 of the second conductivity type in the semiconductor region 72 spaced apart from the drain region 24 and partially surrounding the drain region 24.

摘要翻译： 用于虚拟相位装置的横向溢出漏极包括：第一导电类型的半导体区域72; 形成在半导体区域72中的第一导电类型的漏极区域24; 在半导体区域72中形成并​​围绕漏极区域24的阈值调整区域22; 覆盖并连接到漏区24的电极20，覆盖并与阈值调节区22的至少一部分隔开的电极20; 以及半导体区域72中的第二导电类型的虚拟栅极30和32与漏极区域24间隔开并且部分地围绕漏极区域24。

公开(公告)号：US08928792B1

公开(公告)日：2015-01-06

申请号：US13153369

申请日：2011-06-03

申请人： Jaroslav Hynecek ,  Gennadiy Agranov ,  Xiangli Li ,  Hirofumi Komori ,  Xia Zhao ,  Chung Chun Wan

发明人： Jaroslav Hynecek ,  Gennadiy Agranov ,  Xiangli Li ,  Hirofumi Komori ,  Xia Zhao ,  Chung Chun Wan

IPC分类号： H04N5/335 ,  H04N5/359 ,  H04N5/3745

CPC分类号： H01L27/14612 ,  H01L27/14605 ,  H01L27/14614 ,  H01L27/14645 ,  H01L27/14656 ,  H01L27/14679 ,  H04N5/3591 ,  H04N5/3745

摘要： The invention describes a solid-state CMOS image sensor array and discloses image sensor array pixels with global and rolling shutter capabilities that utilize multiple BCMD transistors for a single photodiode, for charge storage and sensing. Thus, the valuable pixel area saved by employing the BCMD transistor for charge storage and sensing is used by placing several BCMD transistors coupled to one photodiode. This increases the Dynamic Range (DR) of the sensor, since the same photodiode can integrate charge for different integration times, both long and short. This allows sensing of two different image signals from a single pixel without saturation, a low level signal with long integration time followed by a high level signal with short integration time. The signal processing circuits located at the periphery of the array can then process these signals into a single Wide Dynamic Range (WDR) output. Further disclosed is an image sensor array with pixels that use BCMD transistors for charge storage and sensing having multiple concentric gates, which allows changing the conversion gain of the BCMD transistors by applying various biases to the gates. Variable conversion gain is a useful feature when building WDR sensors since low conversion gain and high well capacity allows detection of high level signals and the same structure can be used to detect, at the same time, low level signals with high conversion gain and thus low noise.

摘要翻译： 本发明描述了一种固态CMOS图像传感器阵列，并公开了具有全局和滚动快门功能的图像传感器阵列像素，其利用用于单个光电二极管的多个BCMD晶体管用于电荷存储和感测。 因此，通过使用耦合到一个光电二极管的几个BCMD晶体管来使用通过使用用于电荷存储和感测的BCMD晶体管节省的有价值的像素区域。 这增加了传感器的动态范围（DR），因为相同的光电二极管可以集成不同集成时间的电荷，包括长和短。 这允许感测来自不饱和的单个像素的两个不同图像信号，具有长积分时间的低电平信号，随后是具有短积分时间的高电平信号。 位于阵列外围的信号处理电路然后可以将这些信号处理成单个宽动态范围（WDR）输出。 进一步公开的是具有使用BCMD晶体管的像素的图像传感器阵列，用于具有多个同心门的电荷存储和感测，这允许通过向栅极应用各种偏压来改变BCMD晶体管的转换增益。 可变转换增益是构建WDR传感器的有用特征，因为低转换增益和高容量能够允许检测高电平信号，并且可以使用相同的结构同时检测具有高转换增益的低电平信号，从而低 噪声。

公开(公告)号：US20100188545A1

公开(公告)日：2010-07-29

申请号：US12752279

申请日：2010-04-01

申请人： Eric G. Stevens ,  Hirofumi Komori

发明人： Eric G. Stevens ,  Hirofumi Komori

IPC分类号： H04N5/335 ,  H01L27/146 ,  H01L31/18 ,  H01L27/10

CPC分类号： H01L27/14609 ,  H01L27/1463 ,  H01L27/14643 ,  H01L27/14656

摘要： An image sensor with an image area having a plurality of pixels each having a photodetector of a first conductivity type, the image sensor includes a substrate of the first conductivity type; a first layer of the second conductivity type between the substrate and the photodetectors, spanning the image area and biased at predetermined potential with respect to the substrate for driving excess carriers into the substrate to reduce cross talk; one or more adjacent active electronic components disposed in the first layer within each pixel; and electronic circuitry disposed in the substrate outside of the image area.

摘要翻译： 一种图像传感器，具有具有多个像素的图像区域，每个像素具有第一导电类型的光电检测器，所述图像传感器包括第一导电类型的基板; 在衬底和光电检测器之间的第二导电类型的第一层跨越图像区域并相对于衬底偏置在预定电位，用于将过量的载流子驱动到衬底中以减少串扰; 设置在每个像素内的第一层中的一个或多个相邻的有源电子部件; 以及设置在图像区域外的基板中的电子电路。

公开(公告)号：US07728277B2

公开(公告)日：2010-06-01

申请号：US11455985

申请日：2006-06-20

申请人： Eric G. Stevens ,  Hirofumi Komori

发明人： Eric G. Stevens ,  Hirofumi Komori

IPC分类号： H01L31/00

CPC分类号： H01L27/14609 ,  H01L27/1463 ,  H01L27/14643 ,  H01L27/14656

摘要： An image sensor with an image area having a plurality of pixels with each pixel having a photodetector and a substrate of a first conductivity type and a first layer of a second conductivity type formed between the substrate and the photodetectors. The first layer spans the image area and is biased at predetermined potential with respect to the substrate for driving excess carriers into the substrate to reduce cross talk. One or more adjacent active electronic components can be disposed in the first layer within each pixel and electronic circuitry can be disposed in the substrate outside of the image area.

摘要翻译： 具有图像区域的图像区域具有多个像素，每个像素具有光电检测器和形成在基板和光电检测器之间的第一导电类型的基板和第二导电类型的第一层。 第一层跨越图像区域并相对于衬底偏置在预定电位，用于将过量载流子驱动到衬底中以减少串扰。 一个或多个相邻的有源电子部件可以设置在每个像素内的第一层中，并且电子电路可以设置在图像区域外的基板中。

公开(公告)号：US07144780B2

公开(公告)日：2006-12-05

申请号：US11267397

申请日：2005-11-04

申请人： Hirofumi Komori ,  Mitsuru Yoshikawa

发明人： Hirofumi Komori ,  Mitsuru Yoshikawa

IPC分类号： H01L21/336

CPC分类号： H01L21/823418 ,  H01L21/26586 ,  H01L21/823468 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： The objective of this invention is to provide a semiconductor device and its manufacturing method with which the offset can be kept fixed even in high breakdown voltage MOS transistors, and that can accommodate high voltages for high breakdown voltage MOS transistors and miniaturization of MOS transistors for low voltage drive. Its constitution provides for inner side wall insulating films 14 and 24 and outer side wall insulating films 16 and 26 formed at both sides of the gate electrodes 12 and 22 in both high breakdown voltage transistor TR2 and transistor TR1 for low voltage drive, and heavily doped region 27 is formed in breakdown voltage transistor TR2 using both inner side wall insulating film 24 and outer side wall insulating film 26 as masks so that offset D2 is controlled by the combined widths of the two side wall insulating films. In transistor TR1 for low voltage drive, heavily doped region 15 is formed using only inner side wall insulating film 14 as the mask, and offset d1 is controlled.

摘要翻译： 本发明的目的是提供一种半导体器件及其制造方法，即使在高击穿电压MOS晶体管中也可以保持偏移，并且可以适应高击穿电压MOS晶体管的高电压和低MOS晶体管的小型化 电压驱动。 其构造提供了在低压驱动的高击穿电压晶体管TR2和晶体管TR1中形成在栅电极12和22的两侧的内侧壁绝缘膜14和24以及外侧壁绝缘膜16和26，以及 使用内侧壁绝缘膜24和外侧壁绝缘膜26作为掩模，在击穿电压晶体管TR 2中形成重掺杂区域27，使得偏移量D 2由两个侧壁绝缘膜的组合宽度控制。 在用于低电压驱动的晶体管TR1中，仅使用内侧壁绝缘膜14作为掩模形成重掺杂区域15，并且控制偏移量d 1。

公开(公告)号：US20060057798A1

公开(公告)日：2006-03-16

申请号：US11267397

申请日：2005-11-04

申请人： Hirofumi Komori ,  Mitsuru Yoshikawa

发明人： Hirofumi Komori ,  Mitsuru Yoshikawa

IPC分类号： H01L21/8238 ,  H01L21/336

CPC分类号： H01L21/823418 ,  H01L21/26586 ,  H01L21/823468 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： The objective of this invention is to provide a semiconductor device and its manufacturing method with which the offset can be kept fixed even in high breakdown voltage MOS transistors, and that can accommodate high voltages for high breakdown voltage MOS transistors and miniaturization of MOS transistors for low voltage drive. Its constitution provides for inner side wall insulating films 14 and 24 and outer side wall insulating films 16 and 26 formed at both sides of the gate electrodes 12 and 22 in both high breakdown voltage transistor TR2 and transistor TR1 for low voltage drive, and heavily doped region 27 is formed in breakdown voltage transistor TR2 using both inner side wall insulating film 24 and outer side wall insulating film 26 as masks so that offset D2 is controlled by the combined widths of the two side wall insulating films. In transistor TR1 for low voltage drive, heavily doped region 15 is formed using only inner side wall insulating film 14 as the mask, and offset d1 is controlled.

摘要翻译： 本发明的目的是提供一种半导体器件及其制造方法，即使在高击穿电压MOS晶体管中也可以保持偏移，并且可以适应高击穿电压MOS晶体管的高电压和低MOS晶体管的小型化 电压驱动。 其结构提供了用于低电压驱动的高耐压晶体管TR2和晶体管TR1中形成在栅电极12和22两侧的内侧壁绝缘膜14和24以及外侧壁绝缘膜16和26，以及重掺杂 使用内侧壁绝缘膜24和外侧壁绝缘膜26作为掩模，在击穿电压晶体管TR2中形成区域27，使得偏移D2由两个侧壁绝缘膜的组合宽度控制。 在用于低电压驱动的晶体管TR1中，仅使用内侧壁绝缘膜14作为掩模形成重掺杂区域15，并且控制偏移量d1。