公开(公告)号：US06847080B2

公开(公告)日：2005-01-25

申请号：US10324294

申请日：2002-12-19

申请人： Hirofumi Komori ,  Mitsuru Yoshikawa

发明人： Hirofumi Komori ,  Mitsuru Yoshikawa

IPC分类号： H01L21/8234 ,  H01L21/00 ,  H01L21/311 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/01 ,  H01L27/088 ,  H01L27/092

CPC分类号： H01L21/823418 ,  H01L21/26586 ,  H01L21/823468 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： The objective of this invention is to provide a semiconductor device and its manufacturing method with which the offset can be kept fixed even in high breakdown voltage MOS transistors, and that can accommodate high voltages for high breakdown voltage MOS transistors and miniaturization of MOS transistors for low voltage drive. Its constitution provides for inner side wall insulating films 14 and 24 and outer side wall insulating films 16 and 26 formed at both sides of the gate electrodes 12 and 22 in both high breakdown voltage transistor TR2 and transistor TR1 for low voltage drive, and heavily doped region 27 is formed in breakdown voltage transistor TR2 using both inner side wall insulating film 24 and outer side wall insulating film 26 as masks so that offset d2 is controlled by the combined widths of the two side wall insulating films. In transistor TR1 for low voltage drive, heavily doped region 15 is formed using only inner side wall insulating film 14 as the mask, and offset d1 is controlled.

摘要翻译： 本发明的目的是提供一种半导体器件及其制造方法，即使在高击穿电压MOS晶体管中也可以保持偏移，并且可以适应高击穿电压MOS晶体管的高电压和低MOS晶体管的小型化 电压驱动。 其结构提供了用于低电压驱动的高耐压晶体管TR2和晶体管TR1中形成在栅电极12和22两侧的内侧壁绝缘膜14和24以及外侧壁绝缘膜16和26，以及重掺杂 使用内侧壁绝缘膜24和外侧壁绝缘膜26作为掩模，在击穿电压晶体管TR2中形成区域27，使得偏移d2由两个侧壁绝缘膜的组合宽度控制。 在用于低电压驱动的晶体管TR1中，仅使用内侧壁绝缘膜14作为掩模形成重掺杂区域15，并且控制偏移量d1。

公开(公告)号：US07144780B2

公开(公告)日：2006-12-05

申请号：US11267397

申请日：2005-11-04

申请人： Hirofumi Komori ,  Mitsuru Yoshikawa

发明人： Hirofumi Komori ,  Mitsuru Yoshikawa

IPC分类号： H01L21/336

CPC分类号： H01L21/823418 ,  H01L21/26586 ,  H01L21/823468 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： The objective of this invention is to provide a semiconductor device and its manufacturing method with which the offset can be kept fixed even in high breakdown voltage MOS transistors, and that can accommodate high voltages for high breakdown voltage MOS transistors and miniaturization of MOS transistors for low voltage drive. Its constitution provides for inner side wall insulating films 14 and 24 and outer side wall insulating films 16 and 26 formed at both sides of the gate electrodes 12 and 22 in both high breakdown voltage transistor TR2 and transistor TR1 for low voltage drive, and heavily doped region 27 is formed in breakdown voltage transistor TR2 using both inner side wall insulating film 24 and outer side wall insulating film 26 as masks so that offset D2 is controlled by the combined widths of the two side wall insulating films. In transistor TR1 for low voltage drive, heavily doped region 15 is formed using only inner side wall insulating film 14 as the mask, and offset d1 is controlled.

摘要翻译： 本发明的目的是提供一种半导体器件及其制造方法，即使在高击穿电压MOS晶体管中也可以保持偏移，并且可以适应高击穿电压MOS晶体管的高电压和低MOS晶体管的小型化 电压驱动。 其构造提供了在低压驱动的高击穿电压晶体管TR2和晶体管TR1中形成在栅电极12和22的两侧的内侧壁绝缘膜14和24以及外侧壁绝缘膜16和26，以及 使用内侧壁绝缘膜24和外侧壁绝缘膜26作为掩模，在击穿电压晶体管TR 2中形成重掺杂区域27，使得偏移量D 2由两个侧壁绝缘膜的组合宽度控制。 在用于低电压驱动的晶体管TR1中，仅使用内侧壁绝缘膜14作为掩模形成重掺杂区域15，并且控制偏移量d 1。

公开(公告)号：US20060057798A1

公开(公告)日：2006-03-16

申请号：US11267397

申请日：2005-11-04

申请人： Hirofumi Komori ,  Mitsuru Yoshikawa

发明人： Hirofumi Komori ,  Mitsuru Yoshikawa

IPC分类号： H01L21/8238 ,  H01L21/336

CPC分类号： H01L21/823418 ,  H01L21/26586 ,  H01L21/823468 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： The objective of this invention is to provide a semiconductor device and its manufacturing method with which the offset can be kept fixed even in high breakdown voltage MOS transistors, and that can accommodate high voltages for high breakdown voltage MOS transistors and miniaturization of MOS transistors for low voltage drive. Its constitution provides for inner side wall insulating films 14 and 24 and outer side wall insulating films 16 and 26 formed at both sides of the gate electrodes 12 and 22 in both high breakdown voltage transistor TR2 and transistor TR1 for low voltage drive, and heavily doped region 27 is formed in breakdown voltage transistor TR2 using both inner side wall insulating film 24 and outer side wall insulating film 26 as masks so that offset D2 is controlled by the combined widths of the two side wall insulating films. In transistor TR1 for low voltage drive, heavily doped region 15 is formed using only inner side wall insulating film 14 as the mask, and offset d1 is controlled.

摘要翻译： 本发明的目的是提供一种半导体器件及其制造方法，即使在高击穿电压MOS晶体管中也可以保持偏移，并且可以适应高击穿电压MOS晶体管的高电压和低MOS晶体管的小型化 电压驱动。 其结构提供了用于低电压驱动的高耐压晶体管TR2和晶体管TR1中形成在栅电极12和22两侧的内侧壁绝缘膜14和24以及外侧壁绝缘膜16和26，以及重掺杂 使用内侧壁绝缘膜24和外侧壁绝缘膜26作为掩模，在击穿电压晶体管TR2中形成区域27，使得偏移D2由两个侧壁绝缘膜的组合宽度控制。 在用于低电压驱动的晶体管TR1中，仅使用内侧壁绝缘膜14作为掩模形成重掺杂区域15，并且控制偏移量d1。

公开(公告)号：US20050106827A1

公开(公告)日：2005-05-19

申请号：US10982213

申请日：2004-11-05

申请人： Hirofumi Komori ,  Mitsuru Yoshikawa

发明人： Hirofumi Komori ,  Mitsuru Yoshikawa

IPC分类号： H01L21/8234 ,  H01L21/00 ,  H01L21/311 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/01 ,  H01L27/088 ,  H01L27/092

CPC分类号： H01L21/823418 ,  H01L21/26586 ,  H01L21/823468 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： The objective of this invention is to provide a semiconductor device and its manufacturing method with which the offset can be kept fixed even in high breakdown voltage MOS transistors, and that can accommodate high voltages for high breakdown voltage MOS transistors and miniaturization of MOS transistors for low voltage drive. Its constitution provides for inner side wall insulating films 14 and 24 and outer side wall insulating films 16 and 26 formed at both sides of the gate electrodes 12 and 22 in both high breakdown voltage transistor TR2 and transistor TR1 for low voltage drive, and heavily doped region 27 is formed in breakdown voltage transistor TR2 using both inner side wall insulating film 24 and outer side wall insulating film 26 as masks so that offset d2 is controlled by the combined widths of the two side wall insulating films. In transistor TR1 for low voltage drive, heavily doped region 15 is formed using only inner side wall insulating film 14 as the mask, and offset d1 is controlled.

摘要翻译： 本发明的目的是提供一种半导体器件及其制造方法，即使在高击穿电压MOS晶体管中也可以保持偏移，并且可以适应高击穿电压MOS晶体管的高电压和低MOS晶体管的小型化 电压驱动。 其构造提供了在低压驱动的高击穿电压晶体管TR2和晶体管TR1中形成在栅电极12和22的两侧的内侧壁绝缘膜14和24以及外侧壁绝缘膜16和26，以及 使用内侧壁绝缘膜24和外侧壁绝缘膜26作为掩模，在击穿电压晶体管TR 2中形成重掺杂区27，使得偏移d 2由两个侧壁绝缘膜的组合宽度控制。 在用于低电压驱动的晶体管TR1中，仅使用内侧壁绝缘膜14作为掩模形成重掺杂区域15，并且控制偏移量d 1。

公开(公告)号：US20100052019A1

公开(公告)日：2010-03-04

申请号：US12511446

申请日：2009-07-29

申请人： Hiroshi YAMAMOTO ,  Mitsuru Yoshikawa

发明人： Hiroshi YAMAMOTO ,  Mitsuru Yoshikawa

IPC分类号： H01L29/06 ,  H01L29/78 ,  H01L21/762

CPC分类号： H01L21/76237 ,  H01L21/26513 ,  H01L21/2822 ,  H01L29/42368

摘要： Provided are a semiconductor device and a fabricating method thereof. The semiconductor device includes a substrate having a trench that defines an active region, an isolation layer that buries the trench, a pro-oxidant region formed at an upper corner portion of the trench to enhance oxidation at the upper corner portion of the trench when a gate insulation layer is grown on the active region, and a gate conductive layer formed on the gate insulation layer.

摘要翻译： 提供一种半导体器件及其制造方法。 半导体器件包括具有限定有源区的沟槽的衬底，埋入沟槽的隔离层，形成在沟槽的上角部的促氧化剂区域，以在沟槽的上角部增强氧化 栅极绝缘层在有源区上生长，栅极导电层形成在栅极绝缘层上。

公开(公告)号：US5921125A

公开(公告)日：1999-07-13

申请号：US871950

申请日：1997-06-10

申请人： Toshihiro Inoue ,  Tatsuya Maeda ,  Mitsuru Yoshikawa ,  Chiaki Hatano ,  Yukinori Takano

发明人： Toshihiro Inoue ,  Tatsuya Maeda ,  Mitsuru Yoshikawa ,  Chiaki Hatano ,  Yukinori Takano

IPC分类号： B30B1/26 ,  B30B15/14 ,  H01R43/048 ,  B21B37/00

CPC分类号： H01R43/0488 ,  B30B1/266 ,  B30B15/14 ,  Y10T29/53022 ,  Y10T29/53235

摘要： A method of controlling a terminal press attaching device by providing a elevating crimper for crimping terminals onto exposed conductors of the cables, setting an anvil opposite to the crimper, and elevating the drive means including a servo motor. More specifically, the crimp height for press attached terminals is monitored, a detected height and the predetermined set value are compared to control said drive means such that the detected height is made equal to the set value. Thus, the crimp height of the terminal to be attached (or the crimper height) is automatically and easily adjusted.

摘要翻译： 一种通过提供用于将端子压接在电缆的裸露导体上的升降压接器来设置端子压接装置的方法，设置与压接器相对的砧座，以及升高包括伺服电动机的驱动装置。 更具体地，监视压接附接端子的压接高度，将检测到的高度和预定设定值进行比较以控制所述驱动装置，使得检测到的高度等于设定值。 因此，可以自动且容易地调节要安装的端子的压接高度（或压接器高度）。

公开(公告)号：US08431465B2

公开(公告)日：2013-04-30

申请号：US13331536

申请日：2011-12-20

申请人： Hiroshi Yamamoto ,  Mitsuru Yoshikawa

发明人： Hiroshi Yamamoto ,  Mitsuru Yoshikawa

IPC分类号： H01L21/762

CPC分类号： H01L21/76237 ,  H01L21/26513 ,  H01L21/2822 ,  H01L29/42368

摘要： Provided are a semiconductor device and a fabricating method thereof. The semiconductor device includes a substrate having a trench that defines an active region, an isolation layer that buries the trench, a pro-oxidant region formed at an upper corner portion of the trench to enhance oxidation at the upper corner portion of the trench when a gate insulation layer is grown on the active region, and a gate conductive layer formed on the gate insulation layer.

摘要翻译： 提供一种半导体器件及其制造方法。 半导体器件包括具有限定有源区的沟槽的衬底，埋入沟槽的隔离层，形成在沟槽的上角部的促氧化剂区域，以在沟槽的上角部增强氧化 栅极绝缘层在有源区上生长，栅极导电层形成在栅极绝缘层上。

公开(公告)号：US5926947A

公开(公告)日：1999-07-27

申请号：US810939

申请日：1997-02-27

申请人： Yukinori Takano ,  Mitsuru Yoshikawa ,  Akira Sugiyama

发明人： Yukinori Takano ,  Mitsuru Yoshikawa ,  Akira Sugiyama

IPC分类号： B23P19/00 ,  B23P19/02 ,  H01R13/52 ,  H01R43/00 ,  B23P19/04

CPC分类号： B23P19/02 ,  B23P19/001 ,  H01R43/005 ,  H01R13/5205 ,  Y10T29/49217 ,  Y10T29/4987 ,  Y10T29/53239 ,  Y10T29/53374 ,  Y10T29/53396 ,  Y10T29/53478 ,  Y10T29/53539 ,  Y10T29/53657

摘要： The rubber plug fitting apparatus includes a temporary receiver (4) disposed after the feeder (3); a rubber plug holder (5) pivotable 90 degrees by a first drive means (29); a transfer pin (7) for transferring the rubber plug (2) to the holder (5); a wire guide (11) disposed opposite the holder (5) when the latter is pivotated 90 degrees with the rubber plug held therein, which supports a wire (9); a second drive means (37) for moving the holder in a rubber plug fitting direction; and a third drive means (36) for moving the guide (11) in the same direction. A waterproofing rubber plug is reliably fitted over a wire with high positional accuracy.

摘要翻译： 橡胶塞配合装置包括设置在进料器（3）之后的临时接收器（4）。 通过第一驱动装置（29）可旋转90度的橡胶塞座（5）; 用于将橡胶塞（2）传送到保持器（5）的传送销（7）; 导线器（11），其在所述保持器（5）上与保持在其中的橡胶塞枢转90度时设置在所述保持器（5）相对的位置，所述导线器支撑线材（9）; 第二驱动装置（37），用于沿橡胶塞配合方向移动保持器; 以及用于沿相同方向移动引导件（11）的第三驱动装置（36）。 防水橡胶塞可靠地装在导线上，位置精度高。

公开(公告)号：US20120104504A1

公开(公告)日：2012-05-03

申请号：US13331536

申请日：2011-12-20

申请人： Hiroshi Yamamoto ,  Mitsuru Yoshikawa

发明人： Hiroshi Yamamoto ,  Mitsuru Yoshikawa

IPC分类号： H01L29/78 ,  H01L21/762

CPC分类号： H01L21/76237 ,  H01L21/26513 ,  H01L21/2822 ,  H01L29/42368

摘要： Provided are a semiconductor device and a fabricating method thereof. The semiconductor device includes a substrate having a trench that defines an active region, an isolation layer that buries the trench, a pro-oxidant region formed at an upper corner portion of the trench to enhance oxidation at the upper corner portion of the trench when a gate insulation layer is grown on the active region, and a gate conductive layer formed on the gate insulation layer.

摘要翻译： 提供一种半导体器件及其制造方法。 半导体器件包括具有限定有源区的沟槽的衬底，埋入沟槽的隔离层，形成在沟槽的上角部的促氧化剂区域，以在沟槽的上角部增强氧化 栅极绝缘层在有源区上生长，栅极导电层形成在栅极绝缘层上。

公开(公告)号：US07138689B2

公开(公告)日：2006-11-21

申请号：US10740232

申请日：2003-12-18

申请人： Tsuyoshi Inoue ,  Hiroshi Yamamoto ,  Mitsuru Yoshikawa ,  Saiki Hotate

发明人： Tsuyoshi Inoue ,  Hiroshi Yamamoto ,  Mitsuru Yoshikawa ,  Saiki Hotate

IPC分类号： H01L29/78

CPC分类号： H01L29/6659 ,  H01L21/823418 ,  H01L21/823456 ,  H01L21/823462 ,  H01L21/823468 ,  H01L21/823814 ,  H01L21/82385 ,  H01L21/823857 ,  H01L21/823864 ,  H01L29/6656

摘要： A semiconductor substrate that has a MOS transistor with a high breakdown voltage having double sidewall insulation films and can inhibit negative effects on the electric characteristics and method thereof. The semiconductor device is formed as a transistor with a configuration having gate insulation film 21 and gate electrode 22 formed on semiconductor substrate 10, inner sidewall insulation film 25 formed at least on part of the gate insulation film and on both sides of the gate electrode, outer sidewall insulation film 26 formed at least on part of the gate insulation film and on both sides of the inner sidewall insulation film, low concentration impurity area 23 containing an impurity at a low concentration and formed in the semiconductor substrate in the area underneath the inner sidewall insulation film and the outer sidewall insulation film, and high concentration impurity area 27 containing an impurity at a concentration higher than the low concentration impurity area and formed in the semiconductor substrate in the area underneath both sides of the outer sidewall insulation film.

摘要翻译： 具有具有双层侧壁绝缘膜的具有高击穿电压的MOS晶体管的半导体衬底，并且可以抑制对其电特性及其方法的负面影响。 半导体器件形成为具有形成在半导体衬底10上的栅极绝缘膜21和栅电极22，栅极绝缘膜的至少一部分和栅电极的两侧上形成的内侧壁绝缘膜25的晶体管， 外侧壁绝缘膜26形成在栅极绝缘膜的至少一部分上以及内侧壁绝缘膜的两侧，低浓度杂质区23含有低浓度的杂质，并形成在半导体衬底内的内部区域 侧壁绝缘膜和外侧壁绝缘膜，以及高浓度杂质区域27，其含有浓度高于低浓度杂质区域的杂质，并且形成在半导体衬底中在外侧壁绝缘膜的两侧下方的区域中。