公开(公告)号：US06774673B2

公开(公告)日：2004-08-10

申请号：US10270135

申请日：2002-10-15

申请人： Hiroyoshi Tsuboi ,  Yoshiaki Okuyama

发明人： Hiroyoshi Tsuboi ,  Yoshiaki Okuyama

IPC分类号： H03K19094

CPC分类号： G11C8/08 ,  H03K19/00384 ,  H03K19/01742 ,  H03K19/01855

摘要： A first switch operates in accordance with a control signal and receives an input signal. A voltage conversion circuit converts the input signal having a voltage and transmitted via the first switch to an output signal having a different voltage, and outputs the signal. A second switch connects an output node thereof to a voltage line supplied with a voltage which the voltage conversion circuit should output in accordance with the input signal. Therefore, even the input signal's voltage falling outside the range in which the voltage conversion circuit normally operates, the voltage that the voltage conversion circuit should intrinsically output is supplied to the output node via the second switch. Thus, reliable conversion of the input signal voltage is achieved, resulting in secure operation of the level shifter even during a low power supply voltage. This also prevents malfunction of the semiconductor integrated circuit incorporating such level shifters.

摘要翻译： 第一开关根据控制信号进行操作并接收输入信号。 电压转换电路将具有电压并通过第一开关传输的输入信号转换为具有不同电压的输出信号，并输出该信号。 第二开关将其输出节点连接到提供有电压转换电路应根据输入信号输出的电压的电压线。 因此，即使输入信号的电压落在电压转换电路正常工作的范围之外，电压转换电路本质输出的电压也经由第二开关提供给输出节点。 因此，实现输入信号电压的可靠转换，即使在低电源电压期间也导致电平转换器的安全操作。 这也防止了包含这种电平移位器的半导体集成电路的故障。

公开(公告)号：US06971052B2

公开(公告)日：2005-11-29

申请号：US10255671

申请日：2002-09-27

申请人： Hiroyoshi Tsuboi ,  Shinya Fujioka

发明人： Hiroyoshi Tsuboi ,  Shinya Fujioka

IPC分类号： G01R31/28 ,  G01R31/3181 ,  G01R31/3185 ,  G11C29/00 ,  G11C29/46 ,  H01L21/822 ,  H01L27/04

CPC分类号： G11C29/46 ,  G01R31/3181

摘要： When a test command is received n times, any one of a plurality of tests is started. After the first test is started, any one of the tests is started or terminated every time the test command is received a predetermined number of times which is less than the n times. The number of times of the test command supplied to start or terminate the second and subsequent tests can be less than that of the first test. Accordingly, the time of the second and subsequent tests can be shortened. Since the first test is started only when the test command is received n times, the test is not started accidentally due to noise or the like in normal operation. Namely, the test time can be shortened without decreasing the operation reliability of an integrated circuit. Particularly, when a plurality of tests is executed successively, great benefit can be obtained.

摘要翻译： 当接收到n次测试命令时，开始多个测试中的任何一个。 在第一次测试开始之后，每次接收到测试命令的预定次数小于n次时，任何一个测试都被启动或终止。 提供用于开始或终止第二次和后续测试的测试命令的次数可以小于第一次测试的次数。 因此，可以缩短第二次和随后的测试的时间。 由于仅在接收到n次测试命令时开始第一次测试，因此在正常操作中由于噪音等原因而不会意外启动测试。 也就是说，可以缩短测试时间而不降低集成电路的操作可靠性。 特别地，当连续执行多个测试时，可以获得很大的益处。

公开(公告)号：US06643809B2

公开(公告)日：2003-11-04

申请号：US09764415

申请日：2001-01-19

申请人： Hiroyoshi Tsuboi ,  Shinya Fujioka

发明人： Hiroyoshi Tsuboi ,  Shinya Fujioka

IPC分类号： G01R328

CPC分类号： G11C29/46 ,  G01R31/31701

摘要： A semiconductor device which has a test mode for testing the semiconductor device, is provided with a circuit which generates a first signal based on dummy command signals which are input thereto a plurality of times, and generates a second signal which instructs entry to a corresponding test mode or an exit from a corresponding test mode based on an address signal and the first signal.

摘要翻译： 具有用于测试半导体器件的测试模式的半导体器件被提供有一个电路，该电路基于输入到其中的虚拟命令信号产生第一信号，并产生指示进入相应测试的第二信号 模式或基于地址信号和第一信号从对应的测试模式退出。

公开(公告)号：US06487137B2

公开(公告)日：2002-11-26

申请号：US09924469

申请日：2001-08-09

申请人： Hiroyoshi Tsuboi ,  Shinya Fujioka ,  Koichi Nishimura

发明人： Hiroyoshi Tsuboi ,  Shinya Fujioka ,  Koichi Nishimura

IPC分类号： G11C700

CPC分类号： G11C7/06 ,  G11C29/50

摘要： A semiconductor memory device which includes at least two memory cell arrays, a sense amplifier shared by the memory cell arrays and at least two transfer gates connected respectively between each of the memory cell arrays and the sense amplifier. The semiconductor memory device further includes a first voltage supplier supplying a first voltage to the transfer gates, and a second voltage supplier supplying a second voltage to the transfer gates, with second voltage being higher than the first voltage.

摘要翻译： 一种半导体存储器件，包括至少两个存储单元阵列，由存储单元阵列共享的读出放大器和分别连接在每个存储单元阵列和读出放大器之间的至少两个传输门。 半导体存储器件还包括向传输栅极提供第一电压的第一电压供应器和向转移栅极提供第二电压的第二电压供应器，其中第二电压高于第一电压。