公开(公告)号：US06643809B2

公开(公告)日：2003-11-04

申请号：US09764415

申请日：2001-01-19

申请人： Hiroyoshi Tsuboi ,  Shinya Fujioka

发明人： Hiroyoshi Tsuboi ,  Shinya Fujioka

IPC分类号： G01R328

CPC分类号： G11C29/46 ,  G01R31/31701

摘要： A semiconductor device which has a test mode for testing the semiconductor device, is provided with a circuit which generates a first signal based on dummy command signals which are input thereto a plurality of times, and generates a second signal which instructs entry to a corresponding test mode or an exit from a corresponding test mode based on an address signal and the first signal.

摘要翻译： 具有用于测试半导体器件的测试模式的半导体器件被提供有一个电路，该电路基于输入到其中的虚拟命令信号产生第一信号，并产生指示进入相应测试的第二信号 模式或基于地址信号和第一信号从对应的测试模式退出。

公开(公告)号：US06487137B2

公开(公告)日：2002-11-26

申请号：US09924469

申请日：2001-08-09

申请人： Hiroyoshi Tsuboi ,  Shinya Fujioka ,  Koichi Nishimura

发明人： Hiroyoshi Tsuboi ,  Shinya Fujioka ,  Koichi Nishimura

IPC分类号： G11C700

CPC分类号： G11C7/06 ,  G11C29/50

摘要： A semiconductor memory device which includes at least two memory cell arrays, a sense amplifier shared by the memory cell arrays and at least two transfer gates connected respectively between each of the memory cell arrays and the sense amplifier. The semiconductor memory device further includes a first voltage supplier supplying a first voltage to the transfer gates, and a second voltage supplier supplying a second voltage to the transfer gates, with second voltage being higher than the first voltage.

摘要翻译： 一种半导体存储器件，包括至少两个存储单元阵列，由存储单元阵列共享的读出放大器和分别连接在每个存储单元阵列和读出放大器之间的至少两个传输门。 半导体存储器件还包括向传输栅极提供第一电压的第一电压供应器和向转移栅极提供第二电压的第二电压供应器，其中第二电压高于第一电压。

公开(公告)号：US06971052B2

公开(公告)日：2005-11-29

申请号：US10255671

申请日：2002-09-27

申请人： Hiroyoshi Tsuboi ,  Shinya Fujioka

发明人： Hiroyoshi Tsuboi ,  Shinya Fujioka

IPC分类号： G01R31/28 ,  G01R31/3181 ,  G01R31/3185 ,  G11C29/00 ,  G11C29/46 ,  H01L21/822 ,  H01L27/04

CPC分类号： G11C29/46 ,  G01R31/3181

摘要： When a test command is received n times, any one of a plurality of tests is started. After the first test is started, any one of the tests is started or terminated every time the test command is received a predetermined number of times which is less than the n times. The number of times of the test command supplied to start or terminate the second and subsequent tests can be less than that of the first test. Accordingly, the time of the second and subsequent tests can be shortened. Since the first test is started only when the test command is received n times, the test is not started accidentally due to noise or the like in normal operation. Namely, the test time can be shortened without decreasing the operation reliability of an integrated circuit. Particularly, when a plurality of tests is executed successively, great benefit can be obtained.

摘要翻译： 当接收到n次测试命令时，开始多个测试中的任何一个。 在第一次测试开始之后，每次接收到测试命令的预定次数小于n次时，任何一个测试都被启动或终止。 提供用于开始或终止第二次和后续测试的测试命令的次数可以小于第一次测试的次数。 因此，可以缩短第二次和随后的测试的时间。 由于仅在接收到n次测试命令时开始第一次测试，因此在正常操作中由于噪音等原因而不会意外启动测试。 也就是说，可以缩短测试时间而不降低集成电路的操作可靠性。 特别地，当连续执行多个测试时，可以获得很大的益处。

公开(公告)号：US07903487B2

公开(公告)日：2011-03-08

申请号：US12201922

申请日：2008-08-29

申请人： Shinya Fujioka ,  Tomohiro Kawakubo ,  Koichi Nishimura ,  Kotoku Sato

发明人： Shinya Fujioka ,  Tomohiro Kawakubo ,  Koichi Nishimura ,  Kotoku Sato

IPC分类号： G11C7/00 ,  G11C5/14

CPC分类号： G06F1/3234 ,  G06F1/3203 ,  G06F1/3268 ,  G06F1/3275 ,  G11C5/14 ,  G11C5/145 ,  G11C5/147 ,  G11C11/406 ,  G11C11/40615 ,  G11C14/00 ,  G11C2207/2227 ,  G11C2211/4067 ,  H02M3/07 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D50/20

摘要： An internal voltage generator when activated, generates an internal voltage to be supplied to an internal circuit. Operating the internal voltage generator consumes a predetermined amount of the power. In response to a control signal from the exterior, an entry circuit inactivates the internal voltage generator. When the internal voltage generator is inactivated, the internal voltage is not generated, thereby reducing the power consumption. By the control signal from the exterior, therefore, a chip can easily enter a low power consumption mode. The internal voltage generator is exemplified by a booster for generating the boost voltage of a word line connected with memory cells, a substrate voltage generator for generating a substrate voltage, or a precharging voltage generator for generating the precharging voltage of bit lines to be connected with the memory cells.

摘要翻译： 内部电压发生器激活时，产生内部电压供给内部电路。 操作内部电压发生器消耗预定量的功率。 响应来自外部的控制信号，入口电路使内部电压发生器失活。 内部电压发生器未激活时，不产生内部电压，从而降低功耗。 因此，通过来自外部的控制信号，芯片可以容易地进入低功耗模式。 内部电压发生器的例子是用于产生与存储器单元连接的字线的升压电压的升压器，用于产生衬底电压的衬底电压发生器或用于产生要连接的位线的预充电电压的预充电电压发生器 记忆细胞。

公开(公告)号：US07869296B2

公开(公告)日：2011-01-11

申请号：US11515852

申请日：2006-09-06

申请人： Shinya Fujioka ,  Tomohiro Kawakubo ,  Koichi Nishimura ,  Kotoku Sato

发明人： Shinya Fujioka ,  Tomohiro Kawakubo ,  Koichi Nishimura ,  Kotoku Sato

IPC分类号： G11C7/00 ,  G11C5/14

CPC分类号： G06F1/3234 ,  G06F1/3203 ,  G06F1/3268 ,  G06F1/3275 ,  G11C5/14 ,  G11C5/145 ,  G11C5/147 ,  G11C11/406 ,  G11C11/40615 ,  G11C14/00 ,  G11C2207/2227 ,  G11C2211/4067 ,  H02M3/07 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D50/20

摘要： An internal voltage generator when activated, generates an internal voltage to be supplied to an internal circuit. Operating the internal voltage generator consumes a predetermined amount of the power. In response to a control signal from the exterior, an entry circuit inactivates the internal voltage generator. When the internal voltage generator is inactivated, the internal voltage is not generated, thereby reducing the power consumption. By the control signal from the exterior, therefore, a chip can easily enter a low power consumption mode. The internal voltage generator is exemplified by a booster for generating the boost voltage of a word line connected with memory cells, a substrate voltage generator for generating a substrate voltage, or a precharging voltage generator for generating the precharging voltage of bit lines to be connected with the memory cells.

公开(公告)号：US07848176B2

公开(公告)日：2010-12-07

申请号：US12428828

申请日：2009-04-23

申请人： Hitoshi Ikeda ,  Shinya Fujioka ,  Takahiro Sawamura

发明人： Hitoshi Ikeda ,  Shinya Fujioka ,  Takahiro Sawamura

IPC分类号： G11C8/00

CPC分类号： G11C8/08 ,  G11C7/1018 ,  G11C7/1042 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4085

摘要： A word control circuit activates word lines corresponding to a start row address and a next row address overlappingly in the continuous mode. Accordingly, even in the case where the start address indicates an end memory cell connected to a word line, the switching operation of the word line becomes unnecessary. Memory cells connected to different word lines can be thus accessed in a sequential manner. That is, a controller accessing a semiconductor memory device can access the memory without data interruption. This can prevent the data transfer rate from lowering. Furthermore, it is made unnecessary to form a signal and a control circuit for informing a controller of the fact that a word line is being switched so that the construction of a semiconductor memory device and a control circuit of the controller can be simplified. This results in reduction of the system cost.

摘要翻译： 字控制电路在连续模式下重叠地起动对应于起始行地址和下一行地址的字线。 因此，即使在开始地址指示连接到字线的结束存储单元的情况下，也不需要字线的切换操作。 可以按顺序的方式访问连接到不同字线的存储单元。 也就是说，访问半导体存储器件的控制器可以访问存储器而没有数据中断。 这可以防止数据传输速率降低。 此外，不需要形成信号和控制电路，用于通知控制器正在切换字线的事实，使得可以简化控制器的半导体存储器件和控制电路的结构。 这导致系统成本的降低。

公开(公告)号：US07778099B2

公开(公告)日：2010-08-17

申请号：US12258970

申请日：2008-10-27

申请人： Shinya Fujioka

发明人： Shinya Fujioka

IPC分类号： G11C7/00

CPC分类号： G11C11/406 ,  G11C11/40603 ,  G11C11/40615

摘要： A semiconductor memory is provided, the semiconductor memory including a memory core that includes a plurality of memory cells, a refresh generation unit that generates a refresh request for refreshing the memory cell, a core control unit that performs an access operation in response to an access request, a latency determination unit that activates a latency extension signal upon a conflict between activation of a chip enable signal and the refresh request and that deactivates the latency extension signal in response to deactivation of the chip enable signal, a latency output buffer that outputs the latency extension signal, and a data control unit that changes a latency from the access request to a transfer of data to a data terminal during the activation of the latency extension signal.

摘要翻译： 提供了一种半导体存储器，所述半导体存储器包括包括多个存储单元的存储器核心，产生用于刷新存储单元的刷新请求的刷新生成单元，响应于访问执行访问操作的核心控制单元 请求，等待时间确定单元，其在激活芯片使能信号和刷新请求之间的冲突时激活延迟扩展信号，并且响应于芯片使能信号的去激活而停用延迟扩展信号;等待时间输出缓冲器，其输出 延迟扩展信号，以及数据控制单元，其在等待时间延长信号的激活期间将等待时间从访问请求改变为数据传输到数据终端。

公开(公告)号：US07730232B2

公开(公告)日：2010-06-01

申请号：US11113181

申请日：2005-04-25

申请人： Shinya Fujioka ,  Kotoku Sato ,  Hitoshi Ikeda ,  Yoshiaki Okuyama ,  Jun Ohno

发明人： Shinya Fujioka ,  Kotoku Sato ,  Hitoshi Ikeda ,  Yoshiaki Okuyama ,  Jun Ohno

IPC分类号： G06F13/00

CPC分类号： G06F12/0804 ,  G06F2212/2022 ,  G11C7/1006 ,  G11C11/406 ,  G11C11/40615 ,  G11C16/06 ,  G11C16/3454

摘要： A data transfer method and system are provided that prevent the length of a time required for writing to a flash memory from appearing on the surface as a system operation when the flash memory is used in place of an SRAM. The method of transferring data includes the steps of writing data from a controller to a volatile memory, placing the volatile memory in a transfer state, transferring the data from the volatile memory in the transfer state to a nonvolatile memory, and releasing the volatile memory from the transfer state in response to confirming completion of the transfer of the data.

摘要翻译： 提供了一种数据传输方法和系统，其防止写入闪速存储器所需的时间长度出现在表面上，作为使用闪速存储器代替SRAM的系统操作。 传送数据的方法包括以下步骤：将数据从控制器写入易失性存储器，将易失性存储器置于传送状态，将数据从传送状态的易失性存储器传送到非易失性存储器，并将易失性存储器从 响应于确认完成数据传送的传送状态。

公开(公告)号：US07200059B2

公开(公告)日：2007-04-03

申请号：US11260486

申请日：2005-10-28

申请人： Shinya Fujioka ,  Yoshiaki Okuyama ,  Yasuhiro Takada ,  Tatsuhiro Watanabe ,  Nobumi Kodama

发明人： Shinya Fujioka ,  Yoshiaki Okuyama ,  Yasuhiro Takada ,  Tatsuhiro Watanabe ,  Nobumi Kodama

IPC分类号： G11C29/00

CPC分类号： G11C29/06 ,  G11C29/10 ,  G11C2029/0405 ,  G11C2029/1204 ,  G11C2029/3602

摘要： A burn-in test, including first to sixth steps where voltages are applied for the same lengths of time in each step, is applied to a semiconductor memory having alternately arranged bit line pairs with twist structure where the bit lines cross each other and bit line pairs with non-twist structure where the bit lines are parallel to each other. Since lengths of time in which a stress is applied for all bit lines can be equally set, no deviation occurs in lengths of time where stress is applied between the bit lines. Characteristics of memory cells can be prevented from excessively deteriorating from the burn-in test. Further, the number of bit lines not having stress applied can be minimized in the first to sixth steps. Accordingly, the ratio of the bit lines having stress applied can be increased, which reduces the burn-in test time. Thus, test cost can be reduced.

摘要翻译： 包括在每个步骤中施加相同时间长度的电压的第一至第六步骤的老化测试被施加到具有交替排列的位线对的半导体存储器，其中位线彼此交叉并且位线 对，其中位线彼此平行的非扭转结构。 由于可以对所有位线施加应力的时间长度，所以在位线之间施加应力的时间长度不会发生偏差。 可以防止记忆单元的特性从老化测试过度恶化。 此外，在第一至第六步骤中可以使不具有应力的位线的数量最小化。 因此，可以增加施加了应力的位线的比例，这降低了老化测试时间。 因此，可以降低测试成本。

公开(公告)号：US20070014178A1

公开(公告)日：2007-01-18

申请号：US11515853

申请日：2006-09-06

申请人： Shinya Fujioka ,  Tomohiro Kawakubo ,  Koichi Nishimura ,  Kotoku Sato

发明人： Shinya Fujioka ,  Tomohiro Kawakubo ,  Koichi Nishimura ,  Kotoku Sato

IPC分类号： G11C5/14 ,  G11C7/00 ,  G06F1/00 ,  G06F1/32 ,  G06F1/26

CPC分类号： G06F1/3234 ,  G06F1/3203 ,  G06F1/3268 ,  G06F1/3275 ,  G11C5/14 ,  G11C5/145 ,  G11C5/147 ,  G11C11/406 ,  G11C11/40615 ,  G11C14/00 ,  G11C2207/2227 ,  G11C2211/4067 ,  H02M3/07 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D50/20

摘要： An internal voltage generator when activated, generates an internal voltage to be supplied to an internal circuit. Operating the internal voltage generator consumes a predetermined amount of the power. In response to a control signal from the exterior, an entry circuit inactivates the internal voltage generator. When the internal voltage generator is inactivated, the internal voltage is not generated, thereby reducing the power consumption. By the control signal from the exterior, therefore, a chip can easily enter a low power consumption mode. The internal voltage generator is exemplified by a booster for generating the boost voltage of a word line connected with memory cells, a substrate voltage generator for generating a substrate voltage, or a precharging voltage generator for generating the precharging voltage of bit lines to be connected with the memory cells.

摘要翻译： 内部电压发生器激活时，产生内部电压供给内部电路。 操作内部电压发生器消耗预定量的功率。 响应来自外部的控制信号，入口电路使内部电压发生器失活。 内部电压发生器未激活时，不产生内部电压，从而降低功耗。 因此，通过来自外部的控制信号，芯片可以容易地进入低功耗模式。 内部电压发生器的例子是用于产生与存储器单元连接的字线的升压电压的升压器，用于产生衬底电压的衬底电压发生器或用于产生要连接的位线的预充电电压的预充电电压发生器 记忆细胞。