公开(公告)号：US07876613B2

公开(公告)日：2011-01-25

申请号：US12182274

申请日：2008-07-30

申请人： Sang-Chul Kang ,  Ho-kil Lee ,  Jin-Yub Lee

发明人： Sang-Chul Kang ,  Ho-kil Lee ,  Jin-Yub Lee

IPC分类号： G11C11/34 ,  G11C16/04 ,  G11C16/06

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C16/3454 ,  G11C2211/5621 ,  G11C2211/5642

摘要： Multi-bit flash memory devices are provided. The multi-bit flash memory device includes an array of memory cells and a page buffer block including page buffers. Each of the page buffers has a single latch structure and performs a write operation with respect to memory cells according to loaded data. A buffer random access memory (RAM) is configured to store program data provided from an external host device during a multi-bit program operation. Control logic is provided that is configured to control the page buffer block and the buffer RAM so that program data stored in the buffer RAM is reloaded into the page buffer block whenever data programmed before the multi-bit program operation is compared with data to be currently programmed. The control logic is configured to store data to be programmed next in the buffer RAM before the multi-bit program operation is completed.

摘要翻译： 提供多位闪存设备。 该多位闪存器件包括存储单元阵列和包括页缓冲器的页缓冲块。 每个页面缓冲器具有单个锁存结构，并且根据加载的数据对存储器单元执行写入操作。 缓冲随机存取存储器（RAM）被配置为在多位程序操作期间存储从外部主机设备提供的程序数据。 提供了控制逻辑，其被配置为控制页面缓冲区块和缓冲器RAM，使得存储在缓冲器RAM中的程序数据被重新加载到页面缓冲器块中，每当在多位程序操作之前编程的数据与当前的数据进行比较 程序。 控制逻辑被配置为在多位程序操作完成之前存储要在缓冲RAM中接下来被编程的数据。

公开(公告)号：US20090070523A1

公开(公告)日：2009-03-12

申请号：US12230336

申请日：2008-08-27

申请人： Hyung-Min Kim ,  Ho-Kil Lee ,  Eun-Kyoung Kim

发明人： Hyung-Min Kim ,  Ho-Kil Lee ,  Eun-Kyoung Kim

IPC分类号： G06F12/02 ,  G06F12/00

CPC分类号： G11C11/5628 ,  G11C11/5642 ,  G11C16/22 ,  G11C2211/5641 ,  G11C2216/26

摘要： A flash memory device may include a memory cell array including a plurality of memory blocks and a partition information block, the partition information block storing partition information that indicates a boundary between multi-bit memory blocks and single-bit memory blocks among the memory blocks. The memory device may include a control logic configured to determining whether a memory block that a block address from the outside indicates has a multi-bit form or a single-bit form based on the partition information and to control program and read operations in a multi-bit form or a single-bit form based on a determination result. The control logic automatically programs data in the partition information block according to whether a fuse connected to the control logic fuse is cut or not, the data being used for preventing the partition information block from being programmed or erased.

摘要翻译： 闪存器件可以包括包括多个存储器块和分区信息块的存储单元阵列，该分区信息块存储指示存储器块中的多位存储器块和单位存储器块之间的边界的分区信息。 存储器装置可以包括控制逻辑，该控制逻辑被配置为基于分区信息来确定来自外部的块地址的存储器块是否具有多位形式或单位形式，并且控制多模式中的程序和读操作 - 位形式或基于确定结果的单位形式。 控制逻辑根据连接到控制逻辑熔丝的熔丝是否被切断，自动地对分区信息块中的数据进行编程，该数据用于防止分区信息块被编程或擦除。

公开(公告)号：US07289387B2

公开(公告)日：2007-10-30

申请号：US11383064

申请日：2006-05-12

申请人： Ho-Kil Lee ,  Jin-Yub Lee

发明人： Ho-Kil Lee ,  Jin-Yub Lee

IPC分类号： G11C8/00

CPC分类号： G11C8/08 ,  G11C16/0483 ,  G11C16/08

摘要： A wordline decoder for a non-volatile memory device includes a first inverter to invert a block selection signal into a first inverted result on a first node, a second inverter to invert the signal on the first node into a second inverted result on a second node, a first and a second transistor, each coupled to a power supply, coupled in series between the second node and a third node, a third transistor coupled between the third node and a fourth node having a gate coupled to the third node, a fourth transistor coupled between a high voltage supply and a fifth node having a source coupled to the high voltage supply and a gate coupled to the third node, and a fifth transistor coupled between the fifth node and the third node having a gate coupled to the first node.

摘要翻译： 用于非易失性存储器件的字线解码器包括：第一反相器，用于将块选择信号反转到第一节点上的第一反相结果;第二反相器，用于将第一节点上的信号反转为第二节点上的第二反相结果 ，第一和第二晶体管，每个耦合到电源，串联耦合在第二节点和第三节点之间;第三晶体管，耦合在第三节点和第四节点之间，第四节点具有耦合到第三节点的栅极;第四晶体管，第四晶体管， 耦合在高压电源和耦合到高压电源的源极的第五节点和耦合到第三节点的栅极之间的晶体管，以及耦合在第五节点和第三节点之间的第五晶体管，其具有耦合到第一节点 。

公开(公告)号：US20070133285A1

公开(公告)日：2007-06-14

申请号：US11428816

申请日：2006-07-05

申请人： Ho-Kil Lee ,  Jin-Yub Lee

发明人： Ho-Kil Lee ,  Jin-Yub Lee

IPC分类号： G11C16/04

CPC分类号： G11C16/26 ,  G11C7/1021

摘要： A flash memory includes memory cell array having memory cells divided into sectors, a page buffer block having groups of page buffers corresponding to the sectors, and a page buffer controller configured to control the groups of page buffers individually. In some embodiments, multiple groups of page buffers may be activated simultaneously to access multiple sectors, while page buffer groups for unselected sectors are deactivated.

摘要翻译： 闪速存储器包括具有划分成扇区的存储单元的存储单元阵列，具有与扇区相对应的页缓冲器组的页缓冲块，以及分别控制页缓冲器组的页缓冲器控制器。 在一些实施例中，可以同时激活多组页面缓冲器以访问多个扇区，而对于未选择的扇区的页缓冲器组被去激活。

公开(公告)号：US20060114730A1

公开(公告)日：2006-06-01

申请号：US11282237

申请日：2005-11-18

申请人： Ho-Kil Lee ,  Jin-Yub Lee

发明人： Ho-Kil Lee ,  Jin-Yub Lee

IPC分类号： G11C7/10

CPC分类号： G11C16/10 ,  G11C16/3454 ,  G11C2216/14

摘要： Nonvolatile memory devices include a memory cell array having memory cells arranged in rows and columns, and an address storing unit that is configured to store therein an indicator of an initial column address and an indicator of an end column address, to identify a subset of the columns that extends from the initial column address to the end column address. A program circuit is configured to verify a programming operation for a selected row at the subset of the columns that extends from the initial column address to the end column address. Analogous methods of programming a nonvolatile memory device also may be provided.

摘要翻译： 非易失性存储器件包括具有以行和列排列的存储器单元的存储单元阵列，以及配置为在其中存储初始列地址的指示符和结束列地址的指示符的地址存储单元，以识别 从初始列地址延伸到结束列地址的列。 程序电路被配置为验证在从初始列地址延伸到结束列地址的列的子集处的所选行的编程操作。 也可以提供类似的非易失性存储器件编程方法。

公开(公告)号：US07652948B2

公开(公告)日：2010-01-26

申请号：US11282237

申请日：2005-11-18

申请人： Ho-Kil Lee ,  Jin-Yub Lee

发明人： Ho-Kil Lee ,  Jin-Yub Lee

IPC分类号： G11C8/00

CPC分类号： G11C16/10 ,  G11C16/3454 ,  G11C2216/14

摘要： Nonvolatile memory devices include a memory cell array having memory cells arranged in rows and columns, and an address storing unit that is configured to store therein an indicator of an initial column address and an indicator of an end column address, to identify a subset of the columns that extends from the initial column address to the end column address. A program circuit is configured to verify a programming operation for a selected row at the subset of the columns that extends from the initial column address to the end column address. Analogous methods of programming a nonvolatile memory device also may be provided.

摘要翻译： 非易失性存储器件包括具有以行和列排列的存储器单元的存储单元阵列，以及配置为在其中存储初始列地址的指示符和结束列地址的指示符的地址存储单元，以识别 从初始列地址延伸到结束列地址的列。 程序电路被配置为验证在从初始列地址延伸到结束列地址的列的子集处的所选行的编程操作。 也可以提供类似的非易失性存储器件编程方法。

公开(公告)号：US20080310226A1

公开(公告)日：2008-12-18

申请号：US12182274

申请日：2008-07-30

申请人： Sang-Chul Kang ,  Ho-Kil Lee ,  Jin-Yub Lee

发明人： Sang-Chul Kang ,  Ho-Kil Lee ,  Jin-Yub Lee

IPC分类号： G11C16/04

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C16/3454 ,  G11C2211/5621 ,  G11C2211/5642

摘要： Multi-bit flash memory devices are provided. The multi-bit flash memory device includes an array of memory cells and a page buffer block including page buffers. Each of the page buffers has a single latch structure and performs a write operation with respect to memory cells according to loaded data. A buffer random access memory (RAM) is configured to store program data provided from an external host device during a multi-bit program operation. Control logic is provided that is configured to control the page buffer block and the buffer RAM so that program data stored in the buffer RAM is reloaded into the page buffer block whenever data programmed before the multi-bit program operation is compared with data to be currently programmed. The control logic is configured to store data to be programmed next in the buffer RAM before the multi-bit program operation is completed.

摘要翻译： 提供多位闪存设备。 该多位闪存器件包括存储单元阵列和包括页缓冲器的页缓冲块。 每个页面缓冲器具有单个锁存结构，并且根据加载的数据对存储器单元执行写入操作。 缓冲随机存取存储器（RAM）被配置为在多位程序操作期间存储从外部主机设备提供的程序数据。 提供了控制逻辑，其被配置为控制页面缓冲区块和缓冲器RAM，使得存储在缓冲器RAM中的程序数据被重新加载到页面缓冲器块中，每当在多位程序操作之前编程的数据与当前的数据进行比较 程序。 控制逻辑被配置为在多位程序操作完成之前存储要在缓冲RAM中接下来被编程的数据。

公开(公告)号：US07643339B2

公开(公告)日：2010-01-05

申请号：US11801792

申请日：2007-05-11

申请人： Ho-kil Lee ,  Jin-Yup Lee

发明人： Ho-kil Lee ,  Jin-Yup Lee

IPC分类号： G11C16/04

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C2211/5621 ,  G11C2211/5642 ,  G11C2216/14

摘要： A multi-bit non-volatile memory device is provided. The memory device includes a memory cell array including a plurality of memory cells. A page buffer is electrically coupled to the memory cell array. The page buffer includes a plurality of latches configured to store a first bit of multi-bit data to be written into or read out from one of the plurality of memory cells of the memory cell array. A buffer random access memory (RAM) is electrically coupled to the page buffer. The buffer RAM is configured to store a second bit of the multi-bit data to be written into or read out from one of the plurality of memory cells of the memory cell array. Related systems, memory cards and methods are also provided.

摘要翻译： 提供了一种多位非易失性存储器件。 存储器件包括包括多个存储单元的存储单元阵列。 页面缓冲器电耦合到存储单元阵列。 页面缓冲器包括多个锁存器，其被配置为存储要写入或从存储器单元阵列的多个存储器单元之一读出的多位数据的第一位。 缓冲随机存取存储器（RAM）电耦合到页缓冲器。 缓冲RAM被配置为存储要写入或从存储单元阵列的多个存储单元之一读出的多位数据的第二位。 还提供了相关系统，存储卡和方法。

公开(公告)号：US20070268748A1

公开(公告)日：2007-11-22

申请号：US11801792

申请日：2007-05-11

申请人： Ho-kil Lee ,  Jin-Yup Lee

发明人： Ho-kil Lee ,  Jin-Yup Lee

IPC分类号： G11C14/00 ,  G11C16/04 ,  G11C11/34

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C2211/5621 ,  G11C2211/5642 ,  G11C2216/14

摘要： A multi-bit non-volatile memory device is provided. The memory device includes a memory cell array including a plurality of memory cells. A page buffer is electrically coupled to the memory cell array. The page buffer includes a plurality of latches configured to store a first bit of multi-bit data to be written into or read out from one of the plurality of memory cells of the memory cell array. A buffer random access memory (RAM) is electrically coupled to the page buffer. The buffer RAM is configured to store a second bit of the multi-bit data to be written into or read out from one of the plurality of memory cells of the memory cell array. Related systems, memory cards and methods are also provided.

摘要翻译： 提供了一种多位非易失性存储器件。 存储器件包括包括多个存储单元的存储单元阵列。 页面缓冲器电耦合到存储单元阵列。 页面缓冲器包括多个锁存器，其被配置为存储要写入或从存储器单元阵列的多个存储器单元之一读出的多位数据的第一位。 缓冲随机存取存储器（RAM）电耦合到页缓冲器。 缓冲RAM被配置为存储要写入或从存储单元阵列的多个存储单元之一读出的多位数据的第二位。 还提供了相关系统，存储卡和方法。

公开(公告)号：US20070014184A1

公开(公告)日：2007-01-18

申请号：US11383064

申请日：2006-05-12

申请人： Ho-Kil LEE ,  Jin-Yub LEE

发明人： Ho-Kil LEE ,  Jin-Yub LEE

IPC分类号： G11C8/00

CPC分类号： G11C8/08 ,  G11C16/0483 ,  G11C16/08

摘要： A wordline decoder for a non-volatile memory device includes a first inverter to invert a block selection signal into a first inverted result on a first node, a second inverter to invert the signal on the first node into a second inverted result on a second node, a first and a second transistor, each coupled to a power supply, coupled in series between the second node and a third node, a third transistor coupled between the third node and a fourth node having a gate coupled to the third node, a fourth transistor coupled between a high voltage supply and a fifth node having a source coupled to the high voltage supply and a gate coupled to the third node, and a fifth transistor coupled between the fifth node and the third node having a gate coupled to the first node.

摘要翻译： 用于非易失性存储器件的字线解码器包括：第一反相器，用于将块选择信号反转到第一节点上的第一反相结果;第二反相器，用于将第一节点上的信号反转为第二节点上的第二反相结果 ，第一和第二晶体管，每个耦合到电源，串联耦合在第二节点和第三节点之间;第三晶体管，耦合在第三节点和第四节点之间，第四节点具有耦合到第三节点的栅极;第四晶体管，第四晶体管， 耦合在高压电源和耦合到高压电源的源极的第五节点和耦合到第三节点的栅极之间的晶体管，以及耦合在第五节点和第三节点之间的第五晶体管，其具有耦合到第一节点 。