公开(公告)号：US20120146107A1

公开(公告)日：2012-06-14

申请号：US13274367

申请日：2011-10-17

Applicant: Jong-Won LIM ,  Hokyun Ahn ,  Dong Min Kang ,  Woojin Chang ,  Hae Cheon Kim ,  Eun Soo Nam

Inventor： Jong-Won LIM ,  Hokyun Ahn ,  Dong Min Kang ,  Woojin Chang ,  Hae Cheon Kim ,  Eun Soo Nam

IPC: H01L29/772 ,  H01L21/28

CPC classification number: H01L29/42376 ,  H01L29/2003 ,  H01L29/40 ,  H01L29/402 ,  H01L29/42316 ,  H01L29/66462 ,  H01L29/7787 ,  H01L29/812

Abstract: Disclosed are a semiconductor device and a method of manufacturing the same. In the semiconductor device according to an exemplary embodiment of the present disclosure, at the time of forming a source electrode, a drain electrode, a field plate electrode, and a gate electrode on a substrate having a heterojunction structure such as AlGaN/GaN, the field plate electrode made of the same metal as the gate electrode is formed on the side surface of a second support part positioned below a head part of the gate electrode so as to prevent the gate electrode from collapsing and improve high-frequency and high-voltage characteristic of the semiconductor device.

Abstract translation: 公开了一种半导体器件及其制造方法。 在根据本公开的示例性实施例的半导体器件中，在具有诸如AlGaN / GaN的异质结结构的衬底上形成源电极，漏电极，场板电极和栅电极时， 由与栅电极相同的金属制成的场板电极形成在位于栅电极的头部下方的第二支撑部分的侧表面上，以防止栅电极塌陷并改善高频和高电压 半导体器件的特性。

公开(公告)号：US08053345B2

公开(公告)日：2011-11-08

申请号：US12773216

申请日：2010-05-04

Applicant: Hokyun Ahn ,  Jong-Won Lim ,  Hyung Sup Yoon ,  Woojin Chang ,  Hae Cheon Kim ,  Eun Soo Nam

Inventor： Hokyun Ahn ,  Jong-Won Lim ,  Hyung Sup Yoon ,  Woojin Chang ,  Hae Cheon Kim ,  Eun Soo Nam

IPC: H01L21/3205 ,  H01L21/44

CPC classification number: H01L29/66462

Abstract: Provided is a method for fabricating a field effect transistor. In the method, an active layer and a capping layer are formed on a substrate. A source electrode and a drain electrode is formed on the capping layer. A dielectric interlayer is formed on the substrate, and resist layers having first and second openings with asymmetrical depths are formed on the dielectric interlayer between the source electrode and the drain electrode. The first opening exposes the dielectric interlayer, and the second opening exposes the lowermost of the resist layers. The dielectric interlayer in the bottom of the first opening and the lowermost resist layer under the second opening are simultaneously removed to expose the capping layer to the first opening and expose the dielectric interlayer to the second opening. The capping layer of the first opening is removed to expose the active layer. A metal layer is deposited on the substrate to simultaneously form a gate electrode and a field plate in the first opening and the second opening. The resist layers are removed to lift off the metal layer on the resist layers.

Abstract translation: 提供了一种用于制造场效应晶体管的方法。 在该方法中，在基板上形成有源层和覆盖层。 源极电极和漏电极形成在覆盖层上。 在基板上形成电介质中间层，在源电极和漏极之间的电介质层间形成有具有不对称深度的第一和第二开口的抗蚀剂层。 第一开口露出电介质中间层，第二开口露出最低层的抗蚀剂层。 同时除去第一开口底部的电介质中间层和第二开口下面的最下面的抗蚀剂层，以将覆盖层暴露于第一开口，并将电介质中间层暴露于第二开口。 去除第一开口的覆盖层以暴露活性层。 金属层沉积在基板上，以在第一开口和第二开口中同时形成栅电极和场板。 去除抗蚀剂层以剥离抗蚀剂层上的金属层。

公开(公告)号：US08518794B2

公开(公告)日：2013-08-27

申请号：US12874102

申请日：2010-09-01

Applicant: Hokyun Ahn ,  Jong-Won Lim ,  Hyung Sup Yoon ,  Woojin Chang ,  Hae Cheon Kim

Inventor： Hokyun Ahn ,  Jong-Won Lim ,  Hyung Sup Yoon ,  Woojin Chang ,  Hae Cheon Kim

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/8128 ,  H01L29/42316 ,  H01L29/66863

Abstract: Provided is a semiconductor device. The semiconductor device includes: a substrate; an active layer on the substrate; a capping layer on the active layer; source/drain electrodes on the capping layer; a gate electrode on the active layer; and a first void region on a first sidewall of the gate electrode and a second void region on a second sidewall facing the first sidewall.

Abstract translation: 提供一种半导体器件。 半导体器件包括：衬底; 衬底上的有源层; 活性层上的覆盖层; 覆盖层上的源/漏电极; 有源层上的栅电极; 以及栅电极的第一侧壁上的第一空隙区域和面向第一侧壁的第二侧壁上的第二空隙区域。

公开(公告)号：US08586462B2

公开(公告)日：2013-11-19

申请号：US13307069

申请日：2011-11-30

Applicant: Hokyun Ahn ,  Jong-Won Lim ,  Hyung Sup Yoon ,  Byoung-Gue Min ,  Sang-Heung Lee ,  Hae Cheon Kim ,  Eun Soo Nam

Inventor： Hokyun Ahn ,  Jong-Won Lim ,  Hyung Sup Yoon ,  Byoung-Gue Min ,  Sang-Heung Lee ,  Hae Cheon Kim ,  Eun Soo Nam

IPC: H01L29/808 ,  H01L21/283

CPC classification number: H01L29/7831 ,  H01L29/2003 ,  H01L29/404 ,  H01L29/42316 ,  H01L29/66462 ,  H01L29/66863 ,  H01L29/7787 ,  H01L29/812

Abstract: Disclosed are a method of manufacturing a field-effect transistor. The disclosed method includes: providing a semiconductor substrate; forming a source ohmic metal layer on one side of the semiconductor substrate; forming a drain ohmic metal layer on another side of the semiconductor substrate; forming a gate electrode between the source ohmic metal layer and the drain ohmic metal layer, on an upper portion of the semiconductor substrate; forming an insulating film on the semiconductor substrate's upper portion including the source ohmic metal layer, the drain ohmic metal layer and the gate electrode; and forming a plurality of field electrodes on an upper portion of the insulating film, wherein the insulating film below the respective field electrodes has different thicknesses.

Abstract translation: 公开了一种制造场效晶体管的方法。 所公开的方法包括：提供半导体衬底; 在半导体衬底的一侧上形成源极欧姆金属层; 在所述半导体衬底的另一侧上形成漏极欧姆金属层; 在所述源欧姆金属层和所述漏极欧姆金属层之间形成栅电极，在所述半导体衬底的上部; 在包括源欧姆金属层，漏极欧姆金属层和栅电极的半导体衬底的上部上形成绝缘膜; 以及在绝缘膜的上部形成多个场电极，其中各个场电极下方的绝缘膜具有不同的厚度。

公开(公告)号：US08294521B2

公开(公告)日：2012-10-23

申请号：US12855055

申请日：2010-08-12

Applicant: Dong Min Kang ,  Hong Gu Ji ,  Hokyun Ahn ,  Jong-Won Lim ,  Woojin Chang ,  Sang-Heung Lee ,  Dong-Young Kim ,  Hae Cheon Kim

Inventor： Dong Min Kang ,  Hong Gu Ji ,  Hokyun Ahn ,  Jong-Won Lim ,  Woojin Chang ,  Sang-Heung Lee ,  Dong-Young Kim ,  Hae Cheon Kim

IPC: H03F3/04

CPC classification number: H03F3/24 ,  H03F1/565 ,  H03F3/195 ,  H03F2200/222

Abstract: Provided is a power amplifier including: a depletion mode high electron mobility transistor (D-mode HEMT) configured to amplify a signal inputted to a gate terminal and output the amplified signal through a drain terminal; an input matching circuit configured to serially ground the gate terminal; and a DC bias circuit connected between the drain terminal and a ground. Through the foregoing configuration, the HEMT may be biased only by a single DC bias circuit without any biasing means to provide a negative voltage. Also, superior matching characteristic may be provided in various operation frequency bands through a shunt inductor and a choke inductor.

Abstract translation: 提供了一种功率放大器，包括：耗尽型高电子迁移率晶体管（D模式HEMT），被配置为放大输入到栅极端子的信号，并通过漏极端子输出放大的信号; 输入匹配电路，被配置为使所述栅极端子串联接地; 以及连接在漏极端子和地之间的DC偏置电路。 通过上述配置，HEMT可以仅由单个DC偏置电路偏压而没有任何偏置装置来提供负电压。 此外，可以通过并联电感器和扼流电感器在各种工作频带中提供优异的匹配特性。

公开(公告)号：US06933543B2

公开(公告)日：2005-08-23

申请号：US10874396

申请日：2004-06-22

Applicant: Jae Kyoung Mun ,  Hong Gu Ji ,  Hokyun Ahn ,  Heacheon Kim

Inventor： Jae Kyoung Mun ,  Hong Gu Ji ,  Hokyun Ahn ,  Heacheon Kim

IPC: H01L27/095 ,  H01L29/739 ,  H01L29/778 ,  H01L31/072

CPC classification number: H01L29/7785

Abstract: A high frequency switch device includes an epitaxy substrate that is formed by sequentially stacking an AlGaAs/GaAs superlattic buffer layer, a first Si planar doping layer, an undoped first AlGaAs spacer, an undoped InGaAs layer, an undoped second AlGaAs spacer, a second Si planar doping layer having a doping density greater than that of the first Si planar doping layer, and an undoped GaAs/AlGaAs capping layer on a GaAs semi-insulated substrate. The undoped GaAs/AlGaAs capping layer is formed with a source electrode and a drain electrode that form an ohmic contact with the undoped GaAs/AlGaAs capping layer thereon, and a gate electrode formed between the source electrode and the drain electrode, thereby forming a Schottky contact with the undoped GaAs/AlGaAs capping layer.

Abstract translation: 高频开关器件包括：通过依次层叠AlGaAs / GaAs超缓冲层，第一Si平面掺杂层，未掺杂的第一AlGaAs间隔物，未掺杂的InGaAs层，未掺杂的第二AlGaAs间隔物，第二Si 具有大于第一Si平面掺杂层的掺杂密度的平坦掺杂层和GaAs半绝缘衬底上的未掺杂的GaAs / AlGaAs覆盖层。 未掺杂的GaAs / AlGaAs覆盖层形成有与其上的未掺杂的GaAs / AlGaAs覆盖层形成欧姆接触的源电极和漏电极，以及形成在源电极和漏电极之间的栅电极，由此形成肖特基 与未掺杂的GaAs / AlGaAs覆盖层接触。

公开(公告)号：US08609474B2

公开(公告)日：2013-12-17

申请号：US13274367

申请日：2011-10-17

Applicant: Jong-Won Lim ,  Hokyun Ahn ,  Dong Min Kang ,  Woojin Chang ,  Hae Cheon Kim ,  Eun Soo Nam

Inventor： Jong-Won Lim ,  Hokyun Ahn ,  Dong Min Kang ,  Woojin Chang ,  Hae Cheon Kim ,  Eun Soo Nam

IPC: H01L29/772 ,  H01L21/28 ,  H01L29/423 ,  H01L29/40

CPC classification number: H01L29/42376 ,  H01L29/2003 ,  H01L29/40 ,  H01L29/402 ,  H01L29/42316 ,  H01L29/66462 ,  H01L29/7787 ,  H01L29/812

Abstract: Disclosed are a semiconductor device and a method of manufacturing the same. In the semiconductor device according to an exemplary embodiment of the present disclosure, at the time of forming a source electrode, a drain electrode, a field plate electrode, and a gate electrode on a substrate having a heterojunction structure such as AlGaN/GaN, the field plate electrode made of the same metal as the gate electrode is formed on the side surface of a second support part positioned below a head part of the gate electrode so as to prevent the gate electrode from collapsing and improve high-frequency and high-voltage characteristic of the semiconductor device.

Abstract translation: 公开了一种半导体器件及其制造方法。 在根据本公开的示例性实施例的半导体器件中，在具有诸如AlGaN / GaN的异质结结构的衬底上形成源电极，漏电极，场板电极和栅电极时， 由与栅电极相同的金属制成的场板电极形成在位于栅电极的头部下方的第二支撑部分的侧表面上，以防止栅电极塌陷并改善高频和高电压 半导体器件的特性。

公开(公告)号：US20120153361A1

公开(公告)日：2012-06-21

申请号：US13307069

申请日：2011-11-30

Applicant: Hokyun Ahn ,  Jong-Won Lim ,  Hyung Sup Yoon ,  Byoung-Gue Min ,  Sang-Heung Lee ,  Hae Cheon Kim ,  Eun Soo Nam

Inventor： Hokyun Ahn ,  Jong-Won Lim ,  Hyung Sup Yoon ,  Byoung-Gue Min ,  Sang-Heung Lee ,  Hae Cheon Kim ,  Eun Soo Nam

IPC: H01L21/283 ,  H01L29/808

CPC classification number: H01L29/7831 ,  H01L29/2003 ,  H01L29/404 ,  H01L29/42316 ,  H01L29/66462 ,  H01L29/66863 ,  H01L29/7787 ,  H01L29/812

Abstract: Disclosed are a field-effect transistor and a manufacturing method thereof. The disclosed field-effect transistor includes: a semiconductor substrate; a source ohmic metal layer formed on one side of the semiconductor substrate; a drain ohmic metal layer formed on another side of the semiconductor substrate; a gate electrode formed between the source ohmic metal layer and the drain ohmic metal layer, on an upper portion of the semiconductor substrate; an insulating film formed on the semiconductor substrate's upper portion including the source ohmic metal layer, the drain ohmic metal layer and the gate electrode; and a plurality of field electrodes formed on an upper portion of the insulating film, wherein the insulating film below the respective field electrodes has different thicknesses.

Abstract translation: 公开了场效应晶体管及其制造方法。 所公开的场效应晶体管包括：半导体衬底; 源极欧姆金属层，形成在半导体衬底的一侧上; 形成在所述半导体衬底的另一侧上的漏极欧姆金属层; 在所述源极欧姆金属层和所述漏极欧姆金属层之间形成的栅电极，位于所述半导体衬底的上部; 形成在包括源极欧姆金属层，漏极欧姆金属层和栅电极的半导体衬底的上部上的绝缘膜; 以及形成在绝缘膜的上部的多个场电极，其中，各个场电极下方的绝缘膜具有不同的厚度。

公开(公告)号：US20120142148A1

公开(公告)日：2012-06-07

申请号：US13283626

申请日：2011-10-28

Applicant: Hyung Sup YOON ,  Byoung-Gue Min ,  Hokyun Ahn ,  Sang-Heung Lee ,  Hae Cheon Kim

Inventor： Hyung Sup YOON ,  Byoung-Gue Min ,  Hokyun Ahn ,  Sang-Heung Lee ,  Hae Cheon Kim

IPC: H01L21/335

CPC classification number: H01L29/7783 ,  H01L21/8252 ,  H01L27/0605 ,  H01L29/42316 ,  H01L29/66462

Abstract: Provided are a method of manufacturing a normally-off mode high frequency device structure and a method of simultaneously manufacturing a normally-on mode high frequency device structure and a normally-off mode high frequency device structure on a single substrate.

Abstract translation: 提供一种制造常闭型高频器件结构的方法以及在单个衬底上同时制造常开模式高频器件结构和常关型高频器件结构的方法。

公开(公告)号：US20110143505A1

公开(公告)日：2011-06-16

申请号：US12773216

申请日：2010-05-04

Applicant: Hokyun AHN ,  Jong-Won Lim ,  Hyung Sup Yoon ,  Woojin Chang ,  Hae Cheon Kim ,  Eun Soo Nam

Inventor： Hokyun AHN ,  Jong-Won Lim ,  Hyung Sup Yoon ,  Woojin Chang ,  Hae Cheon Kim ,  Eun Soo Nam

IPC: H01L21/337

CPC classification number: H01L29/66462

Abstract: Provided is a method for fabricating a field effect transistor. In the method, an active layer and a capping layer are formed on a substrate. A source electrode and a drain electrode is formed on the capping layer. A dielectric interlayer is formed on the substrate, and resist layers having first and second openings with asymmetrical depths are formed on the dielectric interlayer between the source electrode and the drain electrode. The first opening exposes the dielectric interlayer, and the second opening exposes the lowermost of the resist layers. The dielectric interlayer in the bottom of the first opening and the lowermost resist layer under the second opening are simultaneously removed to expose the capping layer to the first opening and expose the dielectric interlayer to the second opening. The capping layer of the first opening is removed to expose the active layer. A metal layer is deposited on the substrate to simultaneously form a gate electrode and a field plate in the first opening and the second opening. The resist layers are removed to lift off the metal layer on the resist layers.

Abstract translation: 提供了一种用于制造场效应晶体管的方法。 在该方法中，在基板上形成有源层和覆盖层。 源极电极和漏电极形成在覆盖层上。 在基板上形成电介质中间层，在源电极和漏极之间的电介质层间形成有具有不对称深度的第一和第二开口的抗蚀剂层。 第一开口露出电介质中间层，第二开口露出最低层的抗蚀剂层。 同时除去第一开口底部的电介质中间层和第二开口下面的最下面的抗蚀剂层，以将覆盖层暴露于第一开口，并将电介质中间层暴露于第二开口。 去除第一开口的覆盖层以暴露活性层。 金属层沉积在基板上，以在第一开口和第二开口中同时形成栅电极和场板。 去除抗蚀剂层以剥离抗蚀剂层上的金属层。