公开(公告)号：US06124161A

公开(公告)日：2000-09-26

申请号：US203022

申请日：1998-12-01

Applicant: Horng-Nan Chern ,  Kevin Lin ,  Kun-Chi Lin

Inventor： Horng-Nan Chern ,  Kevin Lin ,  Kun-Chi Lin

IPC: H01L21/02 ,  H01L21/8242 ,  H01L21/8234

CPC classification number: H01L28/84 ,  H01L27/10852

Abstract: A method for forming a hemispherical silicon grain (HSG) layer on a polysilicon electrode is provided. The method is suitable for a substrate, which has a dielectric layer over the substrate with an opening to expose the substrate, and a polysilicon layer is formed over the substrate. A portion of the polysilicon layer is removed above dielectric layer other than the opening region. Each sidewall of the polysilicon layer is slanted so that a trapezoidal polysilicon base is formed. A buffer layer is formed over the trapezoidal polysilicon base. An ion implantation process is performed to form an amorphous silicon layer with sufficient depth on a top surface region of the trapezoidal polysilicon base. The buffer layer includes silicon oxide or silicon nitride. During ion implantation, oxygen or nitrogen elements can also be bombarded into the amorphous silicon layer so as to buffer the amorphous silicon layer to be re-crystallized. A selective HSG layer is formed on the trapezoidal polysilicon electrode base.

Abstract translation: 提供了一种在多晶硅电极上形成半球形硅晶粒（HSG）层的方法。 该方法适合于在衬底上具有介电层的衬底，其具有用于暴露衬底的开口，并且在衬底上形成多晶硅层。 除了开口区域之外，在介电层上除去多晶硅层的一部分。 多晶硅层的每个侧壁都是倾斜的，从而形成梯形多晶硅基底。 缓冲层形成在梯形多晶硅基底上。 执行离子注入工艺以在梯形多晶硅基底的顶表面区域上形成具有足够深度的非晶硅层。 缓冲层包括氧化硅或氮化硅。 在离子注入期间，也可以将氧或氮元素轰击到非晶硅层中，以缓冲非晶硅层再结晶。 在梯形多晶硅电极基体上形成选择性HSG层。

公开(公告)号：US6159806A

公开(公告)日：2000-12-12

申请号：US473985

申请日：1999-12-29

Applicant: Horng-Nan Chern ,  Hsi-Chia Lin ,  Kun-Chi Lin

Inventor： Horng-Nan Chern ,  Hsi-Chia Lin ,  Kun-Chi Lin

IPC: H01L21/8234

CPC classification number: H01L21/823468

Abstract: A method for depositing an oxide layer after spacer formation is disclosed. Owing to an oxide layer after spacer formation, therefore substantially increasing the effective thickness of spacer of the peripheral circuit. The method includes which includes a substrate on which an interior and a peripheral circuit are defined, wherein there is a gate oxide layer formed on the substrate. Sequentially an interior gate and a peripheral gate are formed. Then, N-type ions are implanted into the substrate of the interior and peripheral circuit. Consequently, conformal a second dielectric layer and a third dielectric layer are deposited above the substrate, interior gate, and peripheral gate, wherein second dielectric layer is etched to form a spacer of the interior gate and the peripheral gate. And then N.sup.+ -type ions are implanted into the substrate to form source/drain by using the peripheral gate, the spacer and a portion of the third dielectric layer that runs along the spacer as a mask. Subsequently, a blanket inter-plasma dielectric is deposited above the substrate. Finally, inter-polysilicon dielectric of the interior and peripheral circuit is etched anisotropically to form a plurality of contacts.

Abstract translation: 公开了一种在间隔物形成之后沉积氧化物层的方法。 由于在间隔物形成之后的氧化物层，因此大大增加了外围电路的间隔物的有效厚度。 该方法包括其中限定了内部和外围电路的衬底，其中在衬底上形成有栅极氧化层。 顺序地形成内部门和外围门。 然后，将N型离子注入到内部和外围电路的衬底中。 因此，在衬底，内部栅极和外围栅极上方沉积第二绝缘层和第三介电层，其中第二介电层被蚀刻以形成内部栅极和外围栅极的间隔物。 然后通过使用外围栅极，间隔物和沿着间隔物延伸作为掩模的第三电介质层的一部分，将N +型离子注入到衬底中以形成源极/漏极。 随后，在衬底上方沉积一层等离子体电介质。 最后，各向异性地蚀刻内部和外围电路的多晶硅间电介质以形成多个触点。

公开(公告)号：US6100158A

公开(公告)日：2000-08-08

申请号：US302884

申请日：1999-04-30

Applicant: Tzung-Han Lee ,  Kun-Chi Lin ,  Horng-Nan Chern ,  Alex Hou

Inventor： Tzung-Han Lee ,  Kun-Chi Lin ,  Horng-Nan Chern ,  Alex Hou

IPC: H01L21/762 ,  H01L21/76

CPC classification number: H01L21/76224

Abstract: A method of manufacturing an alignment mark. A substrate having a device region and an alignment mark region is provided. The device region is higher than the alignment mark region. The device region comprises an active region. An isolation structure is formed in the substrate at the edge of the alignment mark region and a first dielectric layer is formed over a portion of the substrate at the alignment mark region, simultaneously. A conductive layer is formed over the substrate. A portion of the conductive layer is removed to expose the first dielectric layer at the alignment mark region. The remaining conductive layer is patterned to form a component at the active region. A second dielectric layer with a smooth surface is formed over the substrate to cover the component. A wire is formed on the second dielectric layer, wherein a distance between the wire and the alignment mark region is larger than a distance between the component and the alignment mark region.

Abstract translation: 制造对准标记的方法。 提供具有器件区域和对准标记区域的衬底。 器件区域高于对准标记区域。 器件区域包括有源区。 在对准标记区域的边缘处的基板中形成隔离结构，同时在对准标记区域的一部分基板上形成第一电介质层。 导电层形成在衬底上。 去除导电层的一部分以在对准标记区域露出第一介电层。 将剩余的导电层图案化以在有源区域形成部件。 在衬底上形成具有光滑表面的第二电介质层以覆盖该部件。 在第二电介质层上形成导线，其中导线与对准标记区域之间的距离大于部件与对准标记区域之间的距离。

公开(公告)号：US06429135B1

公开(公告)日：2002-08-06

申请号：US09754354

申请日：2001-01-05

Applicant: Horng-Nan Chern ,  Kun-Chi Lin

Inventor： Horng-Nan Chern ,  Kun-Chi Lin

IPC: H01L21302

CPC classification number: H01L21/823425 ,  H01L21/28247 ,  H01L21/76829 ,  H01L21/76837 ,  H01L21/823468

Abstract: The semiconductor wafer includes a substrate, a gate positioned on the substrate, a cap layer positioned on top of the gate, and a silicon oxide spacer positioned around both the gate and the cap layer. Firstly, a dielectric layer is formed on the semiconductor wafer to cover the gate. An etching back process is then performed to remove portions of both the dielectric layer and the silicon oxide spacer. Finally, a silicon nitride spacer is formed on the dielectric layer around the cap layer. The silicon nitride spacer is positioned on the surface of the dielectric layer and functions in reducing stress between the silicon nitride spacer and the substrate.

Abstract translation: 半导体晶片包括衬底，位于衬底上的栅极，位于栅极顶部的覆盖层和位于栅极和盖层两侧的氧化硅间隔物。 首先，在半导体晶片上形成介电层以覆盖栅极。 然后进行蚀刻反应处理以去除电介质层和氧化硅间隔物的部分。 最后，在覆盖层周围的电介质层上形成氮化硅间隔物。 氮化硅间隔物定位在电介质层的表面上，起减少氮化硅间隔物和衬底之间的应力的作用。

公开(公告)号：US06255229B1

公开(公告)日：2001-07-03

申请号：US09074780

申请日：1998-05-08

Applicant: Kevin Lin ,  Horng-Nan Chern ,  Kun-Chi Lin

Inventor： Kevin Lin ,  Horng-Nan Chern ,  Kun-Chi Lin

IPC: H01L21469

CPC classification number: H01L21/0214 ,  H01L21/02129 ,  H01L21/02271 ,  H01L21/02362 ,  H01L21/3145 ,  H01L21/31625 ,  H01L21/76801

Abstract: A method for forming a semiconductor dielectric layer comprising the steps of providing a substrate having a plurality of semiconductor devices already formed thereon, and then forming a first dielectric layer over the substrate. Next, a silicon oxy-nitride layer is formed over the first dielectric layer, and finally a second dielectric layer is formed over the silicon oxy-nitride layer.

Abstract translation: 一种形成半导体电介质层的方法，包括以下步骤：提供其上已经形成有多个半导体器件的衬底，然后在衬底上形成第一电介质层。 接下来，在第一介电层上形成氮氧化硅层，最后在氮氧化硅层上形成第二电介质层。

公开(公告)号：US6140202A

公开(公告)日：2000-10-31

申请号：US208739

申请日：1998-12-08

Applicant: Horng-Nan Chern ,  Kun-Chi Lin

Inventor： Horng-Nan Chern ,  Kun-Chi Lin

IPC: H01L21/02 ,  H01L21/3213 ,  H01L21/8242

CPC classification number: H01L28/92 ,  H01L21/32139 ,  H01L27/10852

Abstract: A method for fabricating a double-cylinder capacitor is provided. The double-cylinder capacitor has a storage electrode having dual, concentric cylinder structures. The dielectric layer and the top electrode are formed in sequence over the bottom electrode. The storage area is thus enlarged by the double-cylinder capacitor of the invention. Thus, the capacitance of the capacitor can be effectively increased.

Abstract translation: 提供一种制造双缸电容器的方法。 双缸电容器具有具有双重同心圆筒结构的存储电极。 电介质层和顶电极依次形成在底电极上。 因此，通过本发明的双缸电容器来扩大存储区域。 因此，可以有效地增加电容器的电容。

公开(公告)号：US06238974B1

公开(公告)日：2001-05-29

申请号：US09475212

申请日：1999-12-29

Applicant: Horng-Nan Chern ,  Kevin Lin ,  Kun-Chi Lin

Inventor： Horng-Nan Chern ,  Kevin Lin ,  Kun-Chi Lin

IPC: H01L218242

CPC classification number: H01L28/84 ,  H01L21/76895 ,  H01L27/10852

Abstract: A process of fabricating a bottom electrode for the storage capacitors of DRAM is disclosed. The process includes first forming an insulation layer on the surface of the device substrate, with the insulation layer patterned to form a contact opening that exposes a source/drain region of the memory cell transistor. A first conductive layer then covers the insulation layer and fills into the contact opening, with the first conductive layer contacting the exposed source/drain region. A native oxide layer is then formed on the surface of the first conductive layer. A second electrically conductive layer is then formed and patterned to form a recess substantially above the location of the contact opening in the insulation layer. A layer of HSG—Si then covers the surface of the second conductive layer and the surface of the recess, and the HSG—Si layer and the second conductive layer are patterned to form the bottom electrode of the capacitor. The recess and its covering HSG—Si layer increase the effective surface area of the bottom electrode of the capacitor.

Abstract translation: 公开了制造用于DRAM的存储电容器的底部电极的工艺。 该方法包括首先在器件衬底的表面上形成绝缘层，其中图案化绝缘层以形成暴露存储单元晶体管的源/漏区的接触开口。 然后，第一导电层覆盖绝缘层并填充到接触开口中，第一导电层与暴露的源极/漏极区接触。 然后在第一导电层的表面上形成自然氧化物层。 然后形成第二导电层并图案化以形成基本上在绝缘层中的接触开口位置上方的凹部。 然后，HSG-Si层覆盖第二导电层的表面和凹部的表面，并且对HSG-Si层和第二导电层进行图案化以形成电容器的底部电极。 凹槽及其覆盖的HSG-Si层增加了电容器底部电极的有效表面积。

公开(公告)号：US06417065B1

公开(公告)日：2002-07-09

申请号：US09718190

申请日：2000-11-20

Applicant: King-Lung Wu ,  Kun-Chi Lin

Inventor： King-Lung Wu ,  Kun-Chi Lin

IPC: H01L218242

CPC classification number: H01L27/10855 ,  H01L21/76802 ,  H01L21/76897 ,  H01L27/10885 ,  H01L28/91

Abstract: A method of fabricating a bottom electrode is described. A substrate having a conductive layer therein is provided. A first dielectric layer is formed over the substrate. A conductive plug is formed through the first dielectric layer to electrically couple with the conductive layer. A cap layer is formed over the substrate to cover the conductive plug. An isolation layer is formed over the cap layer. A plurality of bit lines is formed over the isolation layer. A second dielectric layer is formed over the isolation layer. A node contact opening is formed through the second dielectric layer, the bit lines and the isolation layer to expose the cap layer. A conformal isolation layer is formed over the substrate to partially fill the contact node opening. A third dielectric layer having an opening is formed over the substrate. The opening is aligned with the node contact opening. An etching step is performed to remove a portion of the conformal isolation layer exposed by the opening and the cap layer. An isolation spacer remaining from the conformal isolation layer is formed on a sidewall of the contact node opening. A conformal conductive layer is formed in the opening and the node contact opening to make contact with the conductive plug. The third dielectric layer is removed.

Abstract translation: 描述制造底部电极的方法。 提供其中具有导电层的基板。 第一电介质层形成在衬底上。 导电插塞通过第一介电层形成，以与导电层电耦合。 在衬底上形成覆盖导电插塞的覆盖层。 在盖层上方形成隔离层。 多个位线形成在隔离层上。 在隔离层上形成第二电介质层。 通过第二介电层，位线和隔离层形成节点接触开口以露出盖层。 在衬底上形成保形隔离层以部分地填充接触节点开口。 在衬底上形成具有开口的第三电介质层。 开口与节点接触开口对齐。 执行蚀刻步骤以去除由开口和盖层暴露的一部分共形隔离层。 从保形隔离层剩余的隔离间隔物形成在接触节点开口的侧壁上。 在开口和节点接触开口中形成共形导电层以与导电插塞接触。 去除第三电介质层。

公开(公告)号：US06225160B1

公开(公告)日：2001-05-01

申请号：US09295067

申请日：1999-04-20

Applicant: Kuo-Chi Lin ,  Kuo-Tai Huang ,  Da-Wen Shia ,  Kun-Chi Lin

Inventor： Kuo-Chi Lin ,  Kuo-Tai Huang ,  Da-Wen Shia ,  Kun-Chi Lin

IPC: H01L218242

CPC classification number: H01L28/60 ,  H01L21/76895 ,  H01L27/10852 ,  H01L28/84

Abstract: A method of manufacturing a bottom electrode of a capacitor. A first dielectric layer is formed on a substrate. A cap layer is formed on the first dielectric layer. A second dielectric layer is formed on the cap layer. A node contact hole is formed to penetrate through the second dielectric layer, the cap layer and the first dielectric layer. A liner layer is formed on a sidewall of the node contact hole. A restraining layer is formed on the second dielectric layer. A patterned conductive layer is formed on a portion of the restraining layer and fills the node contact hole. A selective hemispherical grained layer is formed on the patterned conductive layer.

Abstract translation: 一种制造电容器的底部电极的方法。 在基板上形成第一电介质层。 在第一电介质层上形成覆盖层。 在盖层上形成第二电介质层。 形成节点接触孔以穿透第二介电层，盖层和第一介电层。 衬垫层形成在节点接触孔的侧壁上。 在第二电介质层上形成限制层。 在限制层的一部分上形成有图案的导电层，并填充节点接触孔。 在图案化的导电层上形成选择性半球形纹理层。

公开(公告)号：US6150223A

公开(公告)日：2000-11-21

申请号：US287881

申请日：1999-04-07

Applicant: Horng-Non Chern ,  Kun-Chi Lin ,  Alex Hou ,  Chien-Hua Tsai ,  Tsu-An Lin

Inventor： Horng-Non Chern ,  Kun-Chi Lin ,  Alex Hou ,  Chien-Hua Tsai ,  Tsu-An Lin

IPC: H01L21/60 ,  H01L21/8234 ,  H01L21/336 ,  H01L21/3205 ,  H01L21/4763 ,  H01L21/76

CPC classification number: H01L21/76897 ,  H01L21/823468

Abstract: A method for forming a different width of gate spacer is disclosed. The method includes firstly forming a gate oxide layer on a semiconductor substrate. A polysilicon layer, a conductive layer, a first dielectric layer are formed in order on the gate oxide layer. The first dielectric layer, the conductive layer, the polysilicon layer, and the gate oxide layer are further etched using them as the interior gate and the peripheral gate. Next, second dielectric layer, third dielectric layer, and fourth dielectric layer are formed over the interior gate and the peripheral gate, and a first photoresist layer abuts the surface of the fourth dielectric layer of the interior circuit. Moreover, etching the fourth dielectric layer of peripheral gate to form a second spacer of peripheral gate, and etching the third dielectric layer of the peripheral gate are undertaken to form a first spacer of the peripheral gate. Removing the first photoresist layer and the fourth dielectric layer of the interior circuit, a fifth dielectric layer is formed on the third dielectric layer of the interior circuit. The fourth dielectric layer and the top surface of the second dielectric layer of the peripheral circuit are removed. The fifth dielectric layer is formed on the first dielectric layer and the third peripheral of the peripheral circuit, and then the second photoresist layer on the fifth dielectric layer, wherein the third photoresist layer is patterned as a bit-line contact via of the interior circuit and the bit-line contact vias of the peripheral circuit. Finally, anisotropically etching the third photoresist layer and the fifth dielectric layer, a bit-line to the substrate contact via and a bit-line to the gate contact via are formed inside the fifth dielectric layer.

Abstract translation: 公开了一种用于形成不同宽度的栅极间隔物的方法。 该方法包括首先在半导体衬底上形成栅氧化层。 在栅极氧化物层上依次形成多晶硅层，导电层，第一介电层。 使用它们作为内部栅极和外围栅极进一步蚀刻第一介电层，导电层，多晶硅层和栅极氧化物层。 接下来，在内部栅极和外围栅极上形成第二电介质层，第三电介质层和第四电介质层，并且第一光致抗蚀剂层邻接内部电路的第四电介质层的表面。 此外，蚀刻外围栅极的第四介电层以形成外围栅极的第二间隔物，并且蚀刻外围栅极的第三介电层以形成外围栅极的第一间隔物。 去除内部电路的第一光致抗蚀剂层和第四电介质层，在内部电路的第三电介质层上形成第五电介质层。 除去第四电介质层和外围电路的第二电介质层的顶表面。 第五电介质层形成在第一电介质层和外围电路的第三外围，然后形成在第五介电层上的第二光致抗蚀剂层，其中第三光致抗蚀剂层被图案化为内部电路的位线接触通孔 和外围电路的位线接触通孔。 最后，在第五介电层内形成各向异性蚀刻第三光致抗蚀剂层和第五电介质层，到基板接触通孔的位线和到栅极接触通孔的位线。