公开(公告)号：US08872269B2

公开(公告)日：2014-10-28

申请号：US13316807

申请日：2011-12-12

申请人： Jen-Hang Yang ,  Chun-Fu Chen ,  Pin-Dai Sue ,  Hui-Zhong Zhuang

发明人： Jen-Hang Yang ,  Chun-Fu Chen ,  Pin-Dai Sue ,  Hui-Zhong Zhuang

IPC分类号： H01L21/70

CPC分类号： H01L21/28008 ,  H01L21/283 ,  H01L21/76895 ,  H01L23/60 ,  H01L27/0207 ,  H01L27/0629 ,  H01L27/0811 ,  H01L2924/0002 ,  H01L2924/00

摘要： An antenna cell for preventing plasma enhanced gate dielectric failures, is provided. The antenna cell design utilizes a polysilicon lead as a gate for a dummy transistor. The polysilicon lead may be one of a group of parallel, nested polysilicon lead. The dummy transistor includes the gate coupled to a substrate maintained at VSS, either directly through a metal lead or indirectly through a tie-low cell. The gate is disposed over a dielectric disposed over a continuous source/drain region in which the source and drain are tied together. A diode is formed with the semiconductor substrate within which it is formed. The source/drain region is coupled to another metal lead which may be an input pin and is coupled to active transistor gates, preventing plasma enhanced gate dielectric damage to the active transistors.

摘要翻译： 提供了一种用于防止等离子体增强的栅极介质故障的天线单元。 天线单元设计利用多晶硅引线作为虚拟晶体管的栅极。 多晶硅引线可以是一组并联的嵌套多晶硅引线之一。 虚拟晶体管包括连接到保持在VSS处的衬底的栅极，直接通过金属引线或间接地通过连接低电池连接。 栅极设置在设置在连续源极/漏极区域上的电介质上，其中源极和漏极连接在一起。 二极管与形成有半导体衬底的半导体衬底形成。 源极/漏极区域耦合到另一个金属引线，金属引线可以是输入引脚并且耦合到有源晶体管栅极，防止等离子体对有源晶体管的栅极介电损伤。

公开(公告)号：US08482314B2

公开(公告)日：2013-07-09

申请号：US13291204

申请日：2011-11-08

申请人： Chun-Fu Chen ,  Hui-Zhong Zhuang ,  Jen-Hang Yang

发明人： Chun-Fu Chen ,  Hui-Zhong Zhuang ,  Jen-Hang Yang

IPC分类号： H03K19/00

CPC分类号： H03K19/1737 ,  H01L27/0207 ,  Y10T29/4913

摘要： A multiplexing circuit includes first and second tri-state inverters coupled to first and second data input nodes, respectively. The first and second tri-state inverters include first and second stacks of transistors, respectively, coupled between power supply and ground nodes. Each stack includes first and second PMOS transistors and first and second NMOS transistors. The first and second stacks include first and second dummy transistors, respectively.

摘要翻译： 复用电路包括分别耦合到第一和第二数据输入节点的第一和第二三态反相器。 第一和第二三态反相器分别包括耦合在电源和接地节点之间的第一和第二晶体管堆叠。 每个堆叠包括第一和第二PMOS晶体管以及第一和第二NMOS晶体管。 第一和第二堆叠分别包括第一和第二虚拟晶体管。

公开(公告)号：US08948510B2

公开(公告)日：2015-02-03

申请号：US13456286

申请日：2012-04-26

申请人： Gwo Giun (Chris) Lee ,  He-Yuan Lin ,  Chun-Fu Chen ,  Ping-Keng Jao

发明人： Gwo Giun (Chris) Lee ,  He-Yuan Lin ,  Chun-Fu Chen ,  Ping-Keng Jao

IPC分类号： G06K9/34 ,  G06K9/00 ,  G06K9/42 ,  G06K9/44 ,  G06T7/00

CPC分类号： G06T7/0071 ,  G06T7/579 ,  G06T2207/10016 ,  G06T2207/10024

摘要： The present invention relates to a method for merging regions in the image/video, capable of merging plural of image regions into an image merging region. In the disclosed method, these image regions are first sequenced basing on their compactness value. Then, one of these image regions is designated as a reference image region, and a merging test process is executed by merging the reference image region with one of the nearby image regions thereof in sequence, for forming a temporal image merging region. Later, the compactness value of the temporal image merging region is compared with the compactness value of the two consisting image regions thereof, respectively. When the compactness value of the temporal image merging region is larger than either one of the compactness value of the two consisting image regions thereof, the temporal image merging region is designated as an image merging region.

摘要翻译： 本发明涉及一种用于合并图像/视频中的区域的方法，其能够将多个图像区域合并成图像合并区域。 在所公开的方法中，这些图像区域首先根据其紧凑度值进行测序。 然后，将这些图像区域中的一个指定为参考图像区域，并且通过依次将参考图像区域与其附近的图像区域中的一个合并来执行合并测试处理，以形成时间图像合成区域。 然后，将时间图像合成区域的紧凑度值分别与其组成的图像区域的紧凑度值进行比较。 当时间图像合并区域的紧凑度值大于其组成图像区域的两个的紧凑度值中的任一个时，时间图像合成区域被指定为图像合并区域。

公开(公告)号：US08445982B2

公开(公告)日：2013-05-21

申请号：US13156933

申请日：2011-06-09

申请人： Chin-Tsan Yeh ,  Chun-Fu Chen ,  Yung-Tai Hung ,  Chin-Ta Su

发明人： Chin-Tsan Yeh ,  Chun-Fu Chen ,  Yung-Tai Hung ,  Chin-Ta Su

IPC分类号： H01L21/76

CPC分类号： H01L21/76232

摘要： A polysilicon structure and method of forming the polysilicon structure are disclosed, where the method includes a two-step deposition and planarization process. The disclosed process reduces the likelihood of defects such as voids, particularly where polysilicon is deposited in a trench having a high aspect ratio. A first polysilicon structure is deposited that includes a trench liner portion and a first upper portion. The trench liner portion only partially fills the trench, while the first upper portion extends over the adjacent field isolation structures. Next, at least a portion of the first upper portion of the first polysilicon structure is removed. A second polysilicon structure is then deposited that includes a trench plug portion and a second upper portion. The trench is filled by the plug portion, while the second upper portion extends over the adjacent field isolation structures. The second upper portion is then removed.

摘要翻译： 公开了多晶硅结构和形成多晶硅结构的方法，其中该方法包括两步沉积和平坦化处理。 所公开的方法降低诸如空隙的缺陷的可能性，特别是在具有高纵横比的沟槽中沉积多晶硅时。 沉积包括沟槽衬垫部分和第一上部部分的第一多晶硅结构。 沟槽衬垫部分仅部分地填充沟槽，而第一上部部分在相邻的隔离结构上延伸。 接下来，去除第一多晶硅结构的第一上部的至少一部分。 然后沉积包括沟槽塞部分和第二上部部分的第二多晶硅结构。 沟槽由插头部分填充，而第二上部部分延伸在相邻的隔离结构上。 然后移除第二个上部。

公开(公告)号：US20120313214A1

公开(公告)日：2012-12-13

申请号：US13156933

申请日：2011-06-09

申请人： Chin-Tsan Yeh ,  Chun-Fu Chen ,  Yung-Tai Hung ,  Chin-Ta Su

发明人： Chin-Tsan Yeh ,  Chun-Fu Chen ,  Yung-Tai Hung ,  Chin-Ta Su

IPC分类号： H01L29/06 ,  H01L21/762

CPC分类号： H01L21/76232

摘要： A polysilicon structure and method of forming the polysilicon structure are disclosed, where the method includes a two-step deposition and planarization process. The disclosed process reduces the likelihood of defects such as voids, particularly where polysilicon is deposited in a trench having a high aspect ratio. A first polysilicon structure is deposited that includes a trench liner portion and a first upper portion. The trench liner portion only partially fills the trench, while the first upper portion extends over the adjacent field isolation structures. Next, at least a portion of the first upper portion of the first polysilicon structure is removed. A second polysilicon structure is then deposited that includes a trench plug portion and a second upper portion. The trench is filled by the plug portion, while the second upper portion extends over the adjacent field isolation structures. The second upper portion is then removed.

摘要翻译： 公开了多晶硅结构和形成多晶硅结构的方法，其中该方法包括两步沉积和平坦化处理。 所公开的方法降低诸如空隙的缺陷的可能性，特别是在具有高纵横比的沟槽中沉积多晶硅时。 沉积包括沟槽衬垫部分和第一上部部分的第一多晶硅结构。 沟槽衬垫部分仅部分地填充沟槽，而第一上部部分在相邻的隔离结构上延伸。 接下来，去除第一多晶硅结构的第一上部的至少一部分。 然后沉积包括沟槽塞部分和第二上部部分的第二多晶硅结构。 沟槽由插塞部分填充，而第二上部部分延伸在相邻的隔离结构上。 然后移除第二个上部。

公开(公告)号：US4091236A

公开(公告)日：1978-05-23

申请号：US720842

申请日：1976-09-07

申请人： Chun-Fu Chen

发明人： Chun-Fu Chen

IPC分类号： H03G5/16 ,  H04R3/02 ,  H04M1/20

CPC分类号： H03G5/16 ,  H04R3/02

摘要： Disclosed is an automatically tunable notch filter and method for suppression of acoustical feedback in an audio signal. The apparatus includes a selectively tunable notch filter having a center frequency which is variable over at least a substantial portion of the audio frequency spectrum. The apparatus receives an audio signal which is substantially non-periodic in the absence of acoustical feedback and substantially periodic with an instantaneous dominant frequency in the presence of the same. The duration of successive periods are monitored and compared by an up/down counter to determine whether the audio input signal is substantially periodic and to determine the instantaneous dominant frequency of such audio signal. Upon detection of an audio signal which is substantially periodic, the notch filter is tuned to the instantaneous dominant frequency so as to suppress the acoustical feedback.

摘要翻译： 公开了一种用于抑制音频信号中的声反馈的自动可调陷波滤波器和方法。 该装置包括可选择的可调陷波滤波器，其具有可在音频频谱的至少大部分上变化的中心频率。 该装置在没有声反馈的情况下接收基本上非周期性的音频信号，并且在存在声音反馈的情况下基本上周期性地具有瞬时主导频率。 监视连续周期的持续时间并通过向上/向下计数器进行比较，以确定音频输入信号是否基本上是周期性的并且确定这种音频信号的瞬时主频。 在检测到基本周期性的音频信号时，将陷波滤波器调谐到瞬时主频，以抑制声反馈。

公开(公告)号：US20120301019A1

公开(公告)日：2012-11-29

申请号：US13456291

申请日：2012-04-26

申请人： Gwo Giun (Chris) Lee ,  He-Yuan Lin ,  Ming-Jiun Wang ,  Chun-Fu Chen

发明人： Gwo Giun (Chris) Lee ,  He-Yuan Lin ,  Ming-Jiun Wang ,  Chun-Fu Chen

IPC分类号： G06K9/34

CPC分类号： G06T7/0071 ,  G06T7/579 ,  G06T2207/10016 ,  G06T2207/10024

摘要： A method for color feature extraction extracts a color feature vector representative of the color of each image pixel contained in an image signal. The method comprises: receiving the image signal; mapping the image signal to a color space model, where the color of each of the plural image pixels is represented by a first parameter, a second parameter, and a third parameter; obtaining an adjusted second parameter; clustering the plural image pixels into plural color regions or plural fuzzy regions of a color plane of the color space model; and designating the color feature vector to each of the plural image pixels based on the clustering result.

摘要翻译： 用于颜色特征提取的方法提取表示包含在图像信号中的每个图像像素的颜色的颜色特征向量。 该方法包括：接收图像信号; 将图像信号映射到颜色空间模型，其中多个图像像素中的每一个的颜色由第一参数，第二参数和第三参数表示; 获得调整后的第二参数; 将所述多个图像像素聚类成所述颜色空间模型的彩色平面的多个颜色区域或多个模糊区域; 以及基于所述聚类结果将所述颜色特征向量指定给所述多个图像像素中的每一个。

公开(公告)号：US07199018B2

公开(公告)日：2007-04-03

申请号：US10837528

申请日：2004-04-30

申请人： Yung-Tai Hung ,  Chun-Fu Chen ,  Yun-Chi Yang ,  Chin-Hsiang Lin ,  Chen-Wei Liao

发明人： Yung-Tai Hung ,  Chun-Fu Chen ,  Yun-Chi Yang ,  Chin-Hsiang Lin ,  Chen-Wei Liao

IPC分类号： H91L21/76

CPC分类号： H01L21/31116 ,  H01L21/31055 ,  H01L21/76224

摘要： The present invention is related to methods of processing a semiconductor device. A plasma vapor deposition process is used to fill a trench with an oxide layer, wherein sharp corners are formed by the oxide layer. A pre-planarization sputtering process is performed to reduce the oxide layer corner sharpness. A planarization process is performed using polishing.

摘要翻译： 本发明涉及半导体器件的处理方法。 使用等离子体气相沉积工艺来填充具有氧化物层的沟槽，其中通过氧化物层形成尖角。 进行预平面化溅射工艺以减少氧化物层拐角锐度。 使用抛光进行平坦化处理。

公开(公告)号：US20050003668A1

公开(公告)日：2005-01-06

申请号：US10837528

申请日：2004-04-30

申请人： Yung-Tai Hung ,  Chun-Fu Chen ,  Yun-Chi Yang ,  Chin-Hsiang Lin ,  Chen-Wei Liao

发明人： Yung-Tai Hung ,  Chun-Fu Chen ,  Yun-Chi Yang ,  Chin-Hsiang Lin ,  Chen-Wei Liao

IPC分类号： H01L21/302 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/762

CPC分类号： H01L21/31116 ,  H01L21/31055 ,  H01L21/76224

摘要： The present invention is related to methods of processing a semiconductor device. A plasma vapor deposition process is used to fill a trench with an oxide layer, wherein sharp corners are formed by the oxide layer. A pre-planarization sputtering process is performed to reduce the oxide layer corner sharpness. A planarization process is performed using polishing.

摘要翻译： 本发明涉及半导体器件的处理方法。 使用等离子体气相沉积工艺来填充具有氧化物层的沟槽，其中通过氧化物层形成尖角。 进行预平面化溅射工艺以减少氧化物层拐角锐度。 使用抛光进行平坦化处理。

公开(公告)号：US09087378B2

公开(公告)日：2015-07-21

申请号：US13537086

申请日：2012-06-29

申请人： Chunhui Cui ,  Chun-Fu Chen ,  Ciao-Siang Siao ,  Gwo Giun Lee ,  Yan Huo

发明人： Chunhui Cui ,  Chun-Fu Chen ,  Ciao-Siang Siao ,  Gwo Giun Lee ,  Yan Huo

IPC分类号： G06T7/00 ,  G06K9/50 ,  G06K9/32

CPC分类号： G06T7/0024 ,  G06K9/50 ,  G06K2009/3291 ,  G06T7/30 ,  G06T2207/10016 ,  G06T2207/30236

摘要： This invention discloses a method for object tracking, including determination of an area scaling ratio of the object in a video image sequence. In one embodiment, a centroid of the object is determined. One or more directed straight lines are selected, each passing through the centroid, extending from an end of the object's boundary to an opposite end thereof, and having a direction that is upward. A length scaling ratio for each directed straight line is determined by: determining a motion vector for each selected pixel on the line; computing a scalar component of the motion vector projected onto the line; estimating a change of the line's length according to the scalar components obtained for all pixels; and determining the length scaling ratio according to the change of the line's length. The area scaling ratio is computed based on the length scaling ratios for all directed straight lines.

摘要翻译： 本发明公开了一种用于对象跟踪的方法，包括确定视频图像序列中的对象的区域缩放比例。 在一个实施例中，确定对象的质心。 选择一个或多个指向的直线，每个直线通过质心，从物体边界的一端延伸到其相对端，并具有向上的方向。 每个指向直线的长度缩放比例由下式确定：确定线上每个所选像素的运动矢量; 计算投影到线上的运动矢量的标量分量; 根据为所有像素获得的标量分量来估计行长度的变化; 并根据线长度的变化来确定长度缩放比例。 基于所有指向直线的长度缩放比率来计算面积缩放比例。