公开(公告)号：US07203124B2

公开(公告)日：2007-04-10

申请号：US10860881

申请日：2004-06-03

申请人： Tae Hyoung Kim ,  Huy Vo ,  Greg Blodgett

发明人： Tae Hyoung Kim ,  Huy Vo ,  Greg Blodgett

IPC分类号： G11C8/00

CPC分类号： G11C8/08

摘要： A negative word line driver employs devices to maintain the potential difference between the active word line signal and the inactive word line signal while reducing the need for a significant negative voltage supply. One form of the negative word line driver employs an isolation element to couple the word line to ground when the inputs to the word line driver indicate the word line should not be active, while the word line is also coupled to the negative voltage supply. Another form of the form of the negative word line driver receives as inputs the voltages to be driven on the word line and can be implemented with fewer transistors but still allows the word line to be driven at a negative voltage with a reduced negative voltage supply.

摘要翻译： 负字线驱动器使用器件来维持有源字线信号和非活动字线信号之间的电位差，同时减少对显着的负电压电源的需要。 当字线驱动器的输入指示字线不应该被激活，同时字线也耦合到负电压源时，一种形式的负字线驱动器采用隔离元件将字线耦合到地。 负字形线驱动器的形式的另一种形式作为输入端接收要在字线上驱动的电压，并且可以用较少的晶体管来实现，但是仍然允许字线在负电压下以负电压供给被驱动。

公开(公告)号：US06809986B2

公开(公告)日：2004-10-26

申请号：US10232953

申请日：2002-08-29

申请人： Tae Hyoung Kim ,  Huy Vo ,  Greg Blodgett

发明人： Tae Hyoung Kim ,  Huy Vo ,  Greg Blodgett

IPC分类号： G11C800

CPC分类号： G11C8/08

摘要： A negative word line driver employs devices to maintain the potential difference between the active word line signal and the inactive word line signal while reducing the need for a significant negative voltage supply. One form of the negative word line driver employs an isolation element to couple the word line to ground when the inputs to the word line driver indicate the word line should not be active, while the word line is also coupled to the negative voltage supply. Another form of the form of the negative word line driver receives as inputs the voltages to be driven on the word line and can be implemented with fewer transistors but still allows the word line to be driven at a negative voltage with a reduced negative voltage supply.

摘要翻译： 负字线驱动器使用器件来维持有源字线信号和非活动字线信号之间的电位差，同时减少对显着的负电压电源的需要。 当字线驱动器的输入指示字线不应该被激活，同时字线也耦合到负电压源时，一种形式的负字线驱动器采用隔离元件将字线耦合到地。 负字形线驱动器的形式的另一种形式作为输入端接收要在字线上驱动的电压，并且可以用较少的晶体管来实现，但是仍然允许字线在负电压下以负电压供给被驱动。

公开(公告)号：US07606102B2

公开(公告)日：2009-10-20

申请号：US11509310

申请日：2006-08-24

申请人： Greg Blodgett

发明人： Greg Blodgett

IPC分类号： G11C17/18

CPC分类号： G11C17/16 ,  G11C29/787 ,  G11C29/812

摘要： A memory chip design methodology is disclosed wherein fuse banks on the memory chip may be implemented without enable fuses. A fuse bank may be enabled by using one or more least significant bits (LSBs) in the memory address stored in the fuse bank, thereby avoiding the need for a separate enable fuse. A reduction in the number of fuses results in space savings on the memory chip real estate and also savings in power consumption because of fewer fuses to be blown and read. With reduced fuse count, the yield of the memory chip's die may also be improved because of less number of defective fuses or failed fuse blows. The use of effective default state inversion for address fuses may further reduce the average number of fuses that need to be blown to repair a given non-redundant memory address. Because of the rules governing abstracts, this abstract should not be used to construe the claims.

摘要翻译： 公开了一种存储器芯片设计方法，其中可以在不使能熔丝的情况下实现存储器芯片上的熔丝组。 可以通过使用存储在熔丝组中的存储器地址中的一个或多个最低有效位（LSB）来使能熔丝组，从而避免需要单独的使能熔丝。 保险丝数量的减少导致存储器芯片空间节省空间，并且由于更少的熔丝被熔化和读取而节省了功率消耗。 由于熔断器计数减少，存储器芯片的裸片的产量也可能由于缺少熔丝数量不足或保险丝熔断失败而得到改善。 对地址熔丝使用有效的默认状态反转可以进一步减少需要熔断的熔断器的平均数，以修复给定的非冗余存储器地址。 由于管理摘要的规则，本摘要不应用于解释索赔。

公开(公告)号：US20060181947A1

公开(公告)日：2006-08-17

申请号：US11402479

申请日：2006-04-11

申请人： Donald Morgan ,  Greg Blodgett

发明人： Donald Morgan ,  Greg Blodgett

IPC分类号： G11C7/00

CPC分类号： G11C11/40622 ,  G11C5/14 ,  G11C11/406 ,  G11C11/408 ,  G11C2211/4061 ,  G11C2211/4067

摘要： A method and system for operating a DRAM device in either a high power, full density mode or a low power, half density mode. In the full density mode, each data bit is stored in a single memory cell, and, in the half density mode, each data bit is stored in two memory cells that are refreshed at the same time to permit a relatively slow refresh rate. When transitioning from the full density mode to the half density mode, data are copied from each row of memory cells storing data to an adjacent row of memory cells. The adjacent row of memory cells are made free to store data from an adjacent row by remapping the most significant bit of the row address to the least significant bit of the row address, and then remapping all of the remaining bits of the row address to the next highest order bit.

公开(公告)号：US20050193241A1

公开(公告)日：2005-09-01

申请号：US11108651

申请日：2005-04-11

申请人： Greg Blodgett

发明人： Greg Blodgett

IPC分类号： G11C29/00 ,  G06F11/00

CPC分类号： G11C29/808 ,  G11C29/846

摘要： A block repair device is used in a Dynamic Random Access Memory (DRAM) having a primary array with a defective cell and a redundant array with a redundant row. The block repair device stores a block repair configuration that determines the dimensions (e.g., the number of rows and columns spanned) of a repair block. Routing circuitry is configured by the stored block repair configuration to output some row and column address bits from received row and column addresses in a selected ratio. Comparison circuitry compares the row and column address bits output by the routing circuitry with the address of the defective cell that defines the repair block. When a match occurs, the comparison circuitry implements a block repair by activating the redundant row and by causing data to be written to or read from the activated redundant row instead of the primary array.

摘要翻译： 在具有具有缺陷单元的主阵列和具有冗余行的冗余阵列的动态随机存取存储器（DRAM）中使用块修复装置。 块修复装置存储确定修复块的尺寸（例如，跨越的行和列的数量）的块修复配置。 通过存储的块修复配置来配置路由电路，以从选定的比率的接收的行和列地址输出一些行和列地址位。 比较电路将路由电路输出的行和列地址位与定义修复块的有缺陷单元的地址进行比较。 当匹配发生时，比较电路通过激活冗余行并且通过使数据被写入或从激活的冗余行而不是主阵列读取来实现块修复。

公开(公告)号：US20050116736A1

公开(公告)日：2005-06-02

申请号：US10726312

申请日：2003-12-01

申请人： Greg Blodgett ,  Christopher Morzano

发明人： Greg Blodgett ,  Christopher Morzano

IPC分类号： H03K19/00 ,  H03K19/003

CPC分类号： H03K19/0005

摘要： An off chip driver impedance adjustment circuit includes a storage circuit adapted to receive and store a drive strength adjustment word. A counter circuit is coupled to the storage circuit to receive the drive strength adjustment word and develops a drive strength count responsive to the drive strength adjustment word. A programmable fuse code to preset the counter. An output driver circuit is coupled to the counter circuit to receive the drive strength count and is adapted to receive a data signal. The output driver circuit develops an output signal on an output responsive to the data signal and adjusts a drive strength as a function of the drive strength count.

摘要翻译： 芯片外驱动器阻抗调整电路包括适于接收和存储驱动强度调节字的存储电路。 计数器电路耦合到存储电路以接收驱动强度调节字，并响应于驱动强度调整字产生驱动强度计数。 可编程保险丝代码来预设计数器。 输出驱动器电路耦合到计数器电路以接收驱动强度计数并且适于接收数据信号。 输出驱动器电路根据数据信号在输出端产生输出信号，并根据驱动强度计数调整驱动强度。

公开(公告)号：US08462570B2

公开(公告)日：2013-06-11

申请号：US12557879

申请日：2009-09-11

申请人： Greg Blodgett

发明人： Greg Blodgett

IPC分类号： G11C7/00 ,  G11C29/00

CPC分类号： G11C17/16 ,  G11C29/787 ,  G11C29/812

摘要： A memory chip design methodology is disclosed wherein fuse banks on the memory chip may be implemented without enable fuses. A fuse bank may be enabled by using one or more least significant bits (LSBs) in the memory address stored in the fuse bank, thereby avoiding the need for a separate enable fuse. A reduction in the number of fuses results in space savings on the memory chip real estate and also savings in power consumption because of fewer fuses to be blown and read. With reduced fuse count, the yield of the memory chip's die may also be improved because of less number of defective fuses or failed fuse blows. The use of effective default state inversion for address fuses may further reduce the average number of fuses that need to be blown to repair a given non-redundant memory address. Because of the rules governing abstracts, this abstract should not be used to construe the claims.

公开(公告)号：US20100182014A1

公开(公告)日：2010-07-22

申请号：US12716822

申请日：2010-03-03

申请人： Raghu Sreeramaneni ,  Vijay Vankayala ,  Greg Blodgett

发明人： Raghu Sreeramaneni ,  Vijay Vankayala ,  Greg Blodgett

IPC分类号： G01R35/00

CPC分类号： H03K19/0005

摘要： Embodiments of the present invention include systems for calibrating an output circuit. A comparator is coupled to a calibration terminal and configured to determine whether the calibration terminal is in a first state coupled to a calibration resistor or in a second state. A calibration circuit is coupled to the calibration terminal and configured to generate a calibration value based in part on the presence or absence of the calibration resistor. An impedance selector is coupled to the calibration circuit, the comparator, and a default calibration value. The impedance selector is configured to select the default calibration value when the comparator indicates the calibration terminal is in the second state and to select the calibration value coupled from the calibration circuit when the comparator indicates the calibration terminal is in the first state.

摘要翻译： 本发明的实施例包括用于校准输出电路的系统。 比较器耦合到校准端子并且被配置为确定校准端子是处于耦合到校准电阻器的第一状态还是处于第二状态。 校准电路耦合到校准端子并且被配置为基于校准电阻器的存在或不存在而产生校准值。 阻抗选择器耦合到校准电路，比较器和默认校准值。 阻抗选择器被配置为当比较器指示校准端处于第二状态时选择默认校准值，并且当比较器指示校准端处于第一状态时选择从校准电路耦合的校准值。

公开(公告)号：US07558125B2

公开(公告)日：2009-07-07

申请号：US11639452

申请日：2006-12-15

申请人： Greg Blodgett

发明人： Greg Blodgett

IPC分类号： G11C7/10

CPC分类号： G11C7/1078 ,  G11C7/02 ,  G11C7/1084 ,  G11C11/4093 ,  H03K5/2481

摘要： An input buffer having a comparator that receives an input signal, a reference signal and a positive feedback. The comparator compares the input signal relative to the reference signal and generates an output signal transitioning between a first logic state and a second logic state responsive to the magnitude of the input signal transitioning through the magnitude of the reference signal. The comparator intensifies the output signal in response to the positive feedback from the output of the comparator while the output signal transitions from the first logic state to the second logic state.

摘要翻译： 具有接收输入信号，参考信号和正反馈的比较器的输入缓冲器。 比较器比较输入信号相对于参考信号，并且响应于输入信号的幅度在参考信号的幅度转变而产生在第一逻辑状态和第二逻辑状态之间转换的输出信号。 当输出信号从第一逻辑状态转换到第二逻辑状态时，比较器响应于来自比较器的输出的正反馈增强输出信号。

公开(公告)号：US07253655B2

公开(公告)日：2007-08-07

申请号：US11218988

申请日：2005-09-01

申请人： Chang Ki Kwon ,  Greg Blodgett

发明人： Chang Ki Kwon ,  Greg Blodgett

IPC分类号： H03K19/003

CPC分类号： H03L7/00 ,  H03K19/00346

摘要： Techniques for controlling a driver to reduce data dependent noise, such as simultaneous switching effects and cross-talk effects. A plurality of drivers may each receive a data segment to transmit and a plurality of data segments that other drivers will transmit. A driver controller may adjust the time at which the data segment is transmitted in response to the plurality of data segments that the other drivers will transmit. The adjustment may compensate for simultaneous switching noise and cross-talk by, for example, delaying the transmission of a data segment or changing the slew rate of the signal carrying the data segment.