公开(公告)号：US07692950B2

公开(公告)日：2010-04-06

申请号：US11969972

申请日：2008-01-07

申请人： Hyoung-Seub Rhie

发明人： Hyoung-Seub Rhie

IPC分类号： G11C11/00

CPC分类号： G11C7/18 ,  H01L27/101

摘要： There is provided a semiconductor memory device including; first and second active areas formed to extend in a first direction on a semiconductor substrate, first and second split word lines formed in a second direction on the semiconductor substrate, a common source line extending between the first and second active areas in the first direction and coupled to the first and second active areas, a first variable resistance element formed on the first active area between the first and second split word lines, a second variable resistance element formed on the second active area between the first and second split word lines, first and second bit lines extending in the first direction and respectively coupled to the first and second variable resistance elements.

摘要翻译： 提供一种半导体存储器件，包括： 第一和第二有源区域形成为在半导体衬底上沿第一方向延伸，在半导体衬底上沿第二方向形成的第一和第二分离字线，在第一方向上在第一和第二有源区域之间延伸的公共源极线，以及 耦合到第一和第二有效区域，形成在第一和第二分割字线之间的第一有效区域上的第一可变电阻元件，形成在第一和第二分割字线之间的第二有效区域上的第二可变电阻元件，第一可变电阻元件 以及在所述第一方向上延伸并且分别耦合到所述第一和第二可变电阻元件的第二位线。

公开(公告)号：US20070195619A1

公开(公告)日：2007-08-23

申请号：US11647672

申请日：2006-12-29

申请人： Hyoung-seub Rhie ,  Yeong-taek Lee

发明人： Hyoung-seub Rhie ,  Yeong-taek Lee

IPC分类号： G11C7/00 ,  G11C29/00

CPC分类号： G11C7/18 ,  G11C11/401 ,  G11C11/404 ,  G11C11/4097 ,  G11C11/565 ,  G11C29/816 ,  G11C2207/002 ,  G11C2207/005 ,  G11C2211/5641

摘要： A memory device includes a first memory array having a plurality of rows and columns of multi-bit DRAM cells therein. A redundant memory array is also provided having a plurality of single-bit memory cells therein. These single-bit memory cells are configured to support replacement of a first plurality of multi-bit memory cells within the first memory array, in response to detecting at least one defective multi-bit memory cell within the first plurality of multi-bit memory cells. This first plurality of multi-bit memory cells may be a column or row of multi-bit memory cells containing at least one defective multi-bit memory cell therein.

摘要翻译： 存储器件包括其中具有多个行和多列DRAM单元的列的第一存储器阵列。 还提供了冗余存储器阵列，其中具有多个单位存储器单元。 响应于检测到第一多个多位存储器单元内的至少一个有缺陷的多位存储器单元，这些单位存储器单元被配置为支持替换第一存储器阵列内的第一多个多位存储器单元 。 该第一多个多位存储器单元可以是其中包含至少一个缺陷多位存储单元的多位存储单元的列或行。

公开(公告)号：US08174865B2

公开(公告)日：2012-05-08

申请号：US12707871

申请日：2010-02-18

申请人： Hyoung-Seub Rhie ,  Suk-Joo Lee

发明人： Hyoung-Seub Rhie ,  Suk-Joo Lee

IPC分类号： G11C11/00

CPC分类号： G11C7/062 ,  G11C11/1673 ,  G11C2207/063

摘要： A memory device includes a plurality of memory bit lines connected to a plurality of memory cells, a plurality of reference bit lines connected to a plurality of reference cells and a reference bit line selection circuit. The memory bit lines has a first pattern and a second pattern, and the first pattern has a first critical dimension (CD) distribution, and the second pattern has a second CD distribution. The reference bit lines have the first pattern and the second pattern. The reference bit line selection circuit provides a reference signal by selecting a reference bit line having a same pattern as a selected memory bit line connected to a memory cell to be read.

摘要翻译： 存储器件包括连接到多个存储器单元的多个存储器位线，连接到多个参考单元的多个参考位线和参考位线选择电路。 存储器位线具有第一图案和第二图案，并且第一图案具有第一临界尺寸（CD）分布，并且第二图案具有第二CD分布。 参考位线具有第一图案和第二图案。 参考位线选择电路通过选择具有与连接到要读取的存储器单元的所选择的存储器位线相同的模式的参考位线来提供参考信号。

公开(公告)号：US07910435B2

公开(公告)日：2011-03-22

申请号：US12349370

申请日：2009-01-06

申请人： Hyoung-Seub Rhie

发明人： Hyoung-Seub Rhie

IPC分类号： H01L21/336

CPC分类号： H01L27/10823 ,  H01L27/10876 ,  H01L29/66666 ,  H01L29/7827

摘要： In a semiconductor device and a method of manufacturing the semiconductor device, the semiconductor device includes a conductive structure, first insulating layers and first conductive layer patterns. The conductive structure includes a first portion, second portions and third portions. The second portions extend in a first direction on the first portion. The second portions are spaced apart from one another in a second direction substantially perpendicular to the first direction. The third portions are provided on the second portions. The third portions are spaced apart from one another in the first and second directions. The first insulating layers cover sidewalls of the second portions. The first conductive layer patterns are provided on the first insulating layers.

摘要翻译： 在半导体器件和半导体器件的制造方法中，半导体器件包括导电结构，第一绝缘层和第一导电层图案。 导电结构包括第一部分，第二部分和第三部分。 第二部分在第一部分上沿第一方向延伸。 第二部分在基本上垂直于第一方向的第二方向上彼此间隔开。 第三部分设置在第二部分上。 第三部分在第一和第二方向上彼此间隔开。 第一绝缘层覆盖第二部分的侧壁。 第一导电层图案设置在第一绝缘层上。

公开(公告)号：US20090296461A1

公开(公告)日：2009-12-03

申请号：US12471630

申请日：2009-05-26

申请人： Sang Beom Kang ,  Hyoung Seub Rhie

发明人： Sang Beom Kang ,  Hyoung Seub Rhie

IPC分类号： G11C11/14 ,  H01L29/82

CPC分类号： H01L27/228 ,  G11C11/16 ,  G11C11/1659 ,  G11C11/1675 ,  G11C19/0841

摘要： Memory devices that include a semiconductor substrate defining a data storage area and a peripheral circuit area. A first magnetic memory device is provided in the peripheral area of the semiconductor substrate and is configured to exchange data signals externally. A second magnetic memory device is provided in the data storage area of the semiconductor substrate and is configured to exchange the data signals with the first magnetic memory device. Each portion of the first magnetic memory device and a portion of the second magnetic memory device include a magnetic tunnel junction structure having at least one magnetic layer. Related data storage devices and systems are also provided.

摘要翻译： 包括限定数据存储区域和外围电路区域的半导体衬底的存储器件。 第一磁存储器件设置在半导体衬底的外围区域中，并被配置为从外部交换数据信号。 第二磁存储器件设置在半导体衬底的数据存储区域中，并被配置为与第一磁存储器件交换数据信号。 第一磁存储器件的每个部分和第二磁存储器件的一部分包括具有至少一个磁性层的磁性隧道结结构。 还提供了相关的数据存储设备和系统。

公开(公告)号：US20070173027A1

公开(公告)日：2007-07-26

申请号：US11582750

申请日：2006-10-18

申请人： Hyoung-Seub Rhie

发明人： Hyoung-Seub Rhie

IPC分类号： H01L21/331

CPC分类号： H01L27/10823 ,  H01L27/10876 ,  H01L29/66666 ,  H01L29/7827

摘要： In a semiconductor device and a method of manufacturing the semiconductor device, the semiconductor device includes a conductive structure, first insulating layers and first conductive layer patterns. The conductive structure includes a first portion, second portions and third portions. The second portions extend in a first direction on the first portion. The second portions are spaced apart from one another in a second direction substantially perpendicular to the first direction. The third portions are provided on the second portions. The third portions are spaced apart from one another in the first and second directions. The first insulating layers cover sidewalls of the second portions. The first conductive layer patterns are provided on the first insulating layers.

摘要翻译： 在半导体器件和半导体器件的制造方法中，半导体器件包括导电结构，第一绝缘层和第一导电层图案。 导电结构包括第一部分，第二部分和第三部分。 第二部分在第一部分上沿第一方向延伸。 第二部分在基本上垂直于第一方向的第二方向上彼此间隔开。 第三部分设置在第二部分上。 第三部分在第一和第二方向上彼此间隔开。 第一绝缘层覆盖第二部分的侧壁。 第一导电层图案设置在第一绝缘层上。

公开(公告)号：US20100208511A1

公开(公告)日：2010-08-19

申请号：US12707871

申请日：2010-02-18

申请人： Hyoung Seub Rhie ,  Suk-Joo Lee

发明人： Hyoung Seub Rhie ,  Suk-Joo Lee

IPC分类号： G11C11/00 ,  G11C7/06

CPC分类号： G11C7/062 ,  G11C11/1673 ,  G11C2207/063

摘要： A memory device includes a plurality of memory bit lines connected to a plurality of memory cells, a plurality of reference bit lines connected to a plurality of reference cells and a reference bit line selection circuit. The memory bit lines has a first pattern and a second pattern, and the first pattern has a first critical dimension (CD) distribution, and the second pattern has a second CD distribution. The reference bit lines have the first pattern and the second pattern. The reference bit line selection circuit provides a reference signal by selecting a reference bit line having a same pattern as a selected memory bit line connected to a memory cell to be read.

摘要翻译： 存储器件包括连接到多个存储器单元的多个存储器位线，连接到多个参考单元的多个参考位线和参考位线选择电路。 存储器位线具有第一图案和第二图案，并且第一图案具有第一临界尺寸（CD）分布，并且第二图案具有第二CD分布。 参考位线具有第一图案和第二图案。 参考位线选择电路通过选择具有与连接到要读取的存储器单元的所选择的存储器位线相同的模式的参考位线来提供参考信号。

公开(公告)号：US20090303631A1

公开(公告)日：2009-12-10

申请号：US12469047

申请日：2009-05-20

申请人： Hyoung-seub RHIE

发明人： Hyoung-seub RHIE

IPC分类号： G11B19/02

CPC分类号： G11C19/0841 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675

摘要： A magnetic racetrack memory device includes; a magnetic track having a plurality of magnetic domains partitioned by at least one magnetic domain wall, a current source applying current to the magnetic track sufficient to move the at least one magnetic domain wall and the plurality of magnetic domains along the magnetic track, a writing device disposed at a first location along the magnetic track and storing write data to the magnetic domains, a reading device disposed at a second location along the magnetic track and retrieving read data from the magnetic domains, and a write-back loop connecting the reading device and the writing device and communicating read data obtained by the reading device to the writing device.

摘要翻译： 磁力跑道存储装置包括： 具有由至少一个磁畴壁分隔的多个磁畴的磁道，电流源向磁道施加足以使所述至少一个磁畴壁和所述多个磁畴沿磁轨移动的写入 设置在沿着磁道的第一位置并将写入数据存储到磁畴的读取装置，设置在沿着磁道的第二位置并从磁畴检索读取数据的读取装置，以及将读取装置 和写入装置，并且将由读取装置获得的读取数据传送给写入装置。

公开(公告)号：US20080165567A1

公开(公告)日：2008-07-10

申请号：US11969972

申请日：2008-01-07

申请人： Hyoung-Seub RHIE

发明人： Hyoung-Seub RHIE

IPC分类号： G11C11/00 ,  G11C7/00

CPC分类号： G11C7/18 ,  H01L27/101

摘要： There is provided a semiconductor memory device including; first and second active areas formed to extend in a first direction on a semiconductor substrate, first and second split word lines formed in a second direction on the semiconductor substrate, a common source line extending between the first and second active areas in the first direction and coupled to the first and second active areas, a first variable resistance element formed on the first active area between the first and second split word lines, a second variable resistance element formed on the second active area between the first and second split word lines, first and second bit lines extending in the first direction and respectively coupled to the first and second variable resistance elements.

摘要翻译： 提供一种半导体存储器件，包括： 形成为在半导体衬底上沿第一方向延伸的第一和第二有源区，在半导体衬底上沿第二方向形成的第一和第二分离字线，在第一方向上在第一和第二有源区之间延伸的公共源极线，以及 耦合到第一和第二有效区域，形成在第一和第二分割字线之间的第一有效区域上的第一可变电阻元件，形成在第一和第二分割字线之间的第二有效区域上的第二可变电阻元件，第一可变电阻元件 以及在所述第一方向上延伸并且分别耦合到所述第一和第二可变电阻元件的第二位线。

公开(公告)号：US07965468B2

公开(公告)日：2011-06-21

申请号：US12469047

申请日：2009-05-20

申请人： Hyoung-seub Rhie

发明人： Hyoung-seub Rhie

IPC分类号： G11B15/18

CPC分类号： G11C19/0841 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675

摘要： A magnetic racetrack memory device includes; a magnetic track having a plurality of magnetic domains partitioned by at least one magnetic domain wall, a current source applying current to the magnetic track sufficient to move the at least one magnetic domain wall and the plurality of magnetic domains along the magnetic track, a writing device disposed at a first location along the magnetic track and storing write data to the magnetic domains, a reading device disposed at a second location along the magnetic track and retrieving read data from the magnetic domains, and a write-back loop connecting the reading device and the writing device and communicating read data obtained by the reading device to the writing device.

摘要翻译： 磁力跑道存储装置包括： 具有由至少一个磁畴壁分隔的多个磁畴的磁道，电流源向磁道施加足以使所述至少一个磁畴壁和所述多个磁畴沿磁轨移动的写入 设置在沿着磁道的第一位置并将写入数据存储到磁畴的读取装置，设置在沿着磁道的第二位置并从磁畴检索读取数据的读取装置，以及将读取装置 和写入装置，并将由读取装置获得的读取数据传送到写入装置。