公开(公告)号：US09490140B2

公开(公告)日：2016-11-08

申请号：US14833311

申请日：2015-08-24

Applicant: Hyun Yong Go ,  Eun Young Lee ,  Jung Geun Jee ,  Eun Yeoung Choi ,  Jin Gyun Kim ,  Hun Hyeong Lim

Inventor： Hyun Yong Go ,  Eun Young Lee ,  Jung Geun Jee ,  Eun Yeoung Choi ,  Jin Gyun Kim ,  Hun Hyeong Lim

IPC: H01L21/3205 ,  H01L21/321 ,  H01L29/49 ,  H01L27/115

CPC classification number: H01L21/321 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/495 ,  H01L29/7827

Abstract: There are provided methods for manufacturing a semiconductor device including providing a substrate including a metal layer including an oxidized surface layer in a heat treatment chamber, generating hydrogen radicals within the heat treatment chamber and reducing the oxidized surface layer of the metal layer using the hydrogen radicals.

Abstract translation: 提供了制造半导体器件的方法，包括在热处理室中提供包括包含氧化表面层的金属层的衬底，在热处理室内产生氢自由基，并使用氢原子还原金属层的氧化表面层 。

公开(公告)号：US09343475B2

公开(公告)日：2016-05-17

申请号：US14155842

申请日：2014-01-15

Applicant: Kyung-Tae Jang ,  Sang-Hoon Lee ,  Ji-Youn Seo ,  Hyun-Yong Go ,  Koong-Hyun Nam ,  Ju-Wan Kim ,  Seung-Mok Shin ,  Myoung-Bum Lee ,  Ji-Woon Im ,  Tae-Jong Han

Inventor： Kyung-Tae Jang ,  Sang-Hoon Lee ,  Ji-Youn Seo ,  Hyun-Yong Go ,  Koong-Hyun Nam ,  Ju-Wan Kim ,  Seung-Mok Shin ,  Myoung-Bum Lee ,  Ji-Woon Im ,  Tae-Jong Han

IPC: H01L21/336 ,  H01L27/115 ,  H01L21/28

CPC classification number: H01L27/11582 ,  H01L21/28282 ,  H01L27/1157

Abstract: In a method of a vertical memory device, insulation layers and sacrificial layers are alternately and repeatedly formed on a substrate. A hole is formed through the insulation layers and the sacrificial layers that expose a top surface of the substrate. Then, an interior portion of the hole may be enlarged. A semiconductor pattern is formed to partially fill the enlarged portion of the hole. A blocking layer, a charge storage layer and a tunnel insulation layer may be formed on a sidewall of the hole and the semiconductor pattern. Then, the tunnel insulation layer, the charge storage layer and the blocking layer are partially removed to expose a top surface of the semiconductor pattern. A channel is formed on the exposed top surface of the semiconductor pattern and the tunnel insulation layer. The sacrificial layers are replaced with gate electrodes.

Abstract translation: 在垂直存储器件的方法中，绝缘层和牺牲层在衬底上交替且重复地形成。 通过绝缘层和暴露衬底顶表面的牺牲层形成一个孔。 然后，可以扩大孔的内部。 半导体图案形成为部分地填充孔的扩大部分。 可以在孔和半导体图案的侧壁上形成阻挡层，电荷存储层和隧道绝缘层。 然后，部分去除隧道绝缘层，电荷存储层和阻挡层，以露出半导体图案的顶表面。 在半导体图案的暴露的顶表面和隧道绝缘层上形成沟道。 牺牲层被栅电极代替。

公开(公告)号：US20150200203A1

公开(公告)日：2015-07-16

申请号：US14155842

申请日：2014-01-15

Applicant: Kyung-Tae Jang ,  Sang-Hoon Lee ,  Ji-Youn Seo ,  Hyun-Yong Go ,  Koong-Hyun Nam ,  Ju-Wan Kim ,  Seung-Mok Shin ,  Myoung-Bum Lee ,  Ji-Woon Im ,  Tae-Jong Han

Inventor： Kyung-Tae Jang ,  Sang-Hoon Lee ,  Ji-Youn Seo ,  Hyun-Yong Go ,  Koong-Hyun Nam ,  Ju-Wan Kim ,  Seung-Mok Shin ,  Myoung-Bum Lee ,  Ji-Woon Im ,  Tae-Jong Han

IPC: H01L27/115 ,  H01L29/66 ,  H01L29/788 ,  H01L21/28

CPC classification number: H01L27/11582 ,  H01L21/28282 ,  H01L27/1157

Abstract: In a method of a vertical memory device, insulation layers and sacrificial layers are alternately and repeatedly formed on a substrate. A hole is formed through the insulation layers and the sacrificial layers that expose a top surface of the substrate. Then, an interior portion of the hole may be enlarged. A semiconductor pattern is formed to partially fill the enlarged portion of the hole. A blocking layer, a charge storage layer and a tunnel insulation layer may be formed on a sidewall of the hole and the semiconductor pattern. Then, the tunnel insulation layer, the charge storage layer and the blocking layer are partially removed to expose a top surface of the semiconductor pattern. A channel is formed on the exposed top surface of the semiconductor pattern and the tunnel insulation layer. The sacrificial layers are replaced with gate electrodes.

Abstract translation: 在垂直存储器件的方法中，绝缘层和牺牲层在衬底上交替且重复地形成。 通过绝缘层和暴露衬底顶表面的牺牲层形成一个孔。 然后，可以扩大孔的内部。 半导体图案形成为部分地填充孔的扩大部分。 可以在孔和半导体图案的侧壁上形成阻挡层，电荷存储层和隧道绝缘层。 然后，部分去除隧道绝缘层，电荷存储层和阻挡层，以露出半导体图案的顶表面。 在半导体图案的暴露的顶表面和隧道绝缘层上形成沟道。 牺牲层被栅电极代替。

公开(公告)号：US20160064227A1

公开(公告)日：2016-03-03

申请号：US14833311

申请日：2015-08-24

Applicant: Hyun Yong GO ,  Eun Young LEE ,  Jung Geun JEE ,  Eun Yeoung CHOI ,  Jin Gyun KIM ,  Hun Hyeong LIM

Inventor： Hyun Yong GO ,  Eun Young LEE ,  Jung Geun JEE ,  Eun Yeoung CHOI ,  Jin Gyun KIM ,  Hun Hyeong LIM

IPC: H01L21/28 ,  H01L21/321 ,  H01L29/49

CPC classification number: H01L21/321 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/495 ,  H01L29/7827

Abstract: There are provided methods for manufacturing a semiconductor device including providing a substrate including a metal layer including an oxidized surface layer in a heat treatment chamber, generating hydrogen radicals within the heat treatment chamber and reducing the oxidized surface layer of the metal layer using the hydrogen radicals.

Abstract translation: 提供了制造半导体器件的方法，包括在热处理室中提供包括包含氧化表面层的金属层的衬底，在热处理室内产生氢自由基，并使用氢原子还原金属层的氧化表面层 。