公开(公告)号：US10008410B2

公开(公告)日：2018-06-26

申请号：US15464532

申请日：2017-03-21

申请人： Kwang Chul Park ,  Ji Woon Im ,  Dai Hong Kim ,  Il Woo Kim ,  Hyun Seok Lim

发明人： Kwang Chul Park ,  Ji Woon Im ,  Dai Hong Kim ,  Il Woo Kim ,  Hyun Seok Lim

IPC分类号： H01L21/768 ,  H01L21/02 ,  H01L21/311 ,  H01L21/28 ,  H01L27/1157 ,  H01L27/11582 ,  C23C16/48 ,  C23C16/50 ,  C23C16/54

CPC分类号： H01L21/76825 ,  C23C16/45523 ,  C23C16/482 ,  C23C16/50 ,  C23C16/54 ,  C23C16/56 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02274 ,  H01L21/02348 ,  H01L21/31111 ,  H01L21/76802 ,  H01L21/76877 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/40117

摘要： A deposition apparatus includes a chamber, a plate in the chamber and configured support a substrate, a deposition unit configured to perform a deposition process in-situ in the chamber, and a UV annealing unit configured to perform a first ultraviolet (UV) and a second ultraviolet (UV) annealing process in-situ in the chamber. The deposition process may include sequentially depositing a first sacrificial layer, a first oxide layer, a second sacrificial layer and a second oxide layer on the substrate. The first UV annealing process may be performed on the first oxide layer after the first oxide layer is deposited. The second UV annealing process may be different from the first UV annealing process and may be performed on the second oxide layer after the second oxide layer is deposited.

公开(公告)号：US20140048945A1

公开(公告)日：2014-02-20

申请号：US13927914

申请日：2013-06-26

申请人： Jong-Heun LIM ,  Hyo-Jung KIM ,  Ji-Woon IM ,  Kyung-Hyun KIM

发明人： Jong-Heun LIM ,  Hyo-Jung KIM ,  Ji-Woon IM ,  Kyung-Hyun KIM

IPC分类号： H01L23/48

CPC分类号： H01L23/48 ,  H01L27/11575 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

摘要： A nonvolatile memory device including a substrate which includes a cell array region and a connection region, an electrode structure formed on the cell array region and the connection region and including a plurality of laminated electrodes, a first recess formed in the electrode structure on the connection region and disposed between the cell array region and a second recess formed in the electrode structure on the connection region, and a plurality of vertical wirings formed on the plurality of electrodes exposed by the first recess.

摘要翻译： 一种非易失性存储器件，包括：包括单元阵列区域和连接区域的基板;形成在单元阵列区域上的电极结构和连接区域，并且包括多个层压电极;形成在电极结构中的第一凹部， 并且布置在单元阵列区域和形成在连接区域上的电极结构中的第二凹槽之间，以及形成在由第一凹部暴露的多个电极上的多个垂直布线。

公开(公告)号：US20080044775A1

公开(公告)日：2008-02-21

申请号：US11667600

申请日：2005-11-11

申请人： Seung-Hun Hong ,  Min-Baek Lee ,  Ji-Woon Im

发明人： Seung-Hun Hong ,  Min-Baek Lee ,  Ji-Woon Im

IPC分类号： G03F7/00

CPC分类号： B05D1/185 ,  B05D3/002 ,  B81C3/002 ,  B82Y30/00 ,  B82Y40/00

摘要： The present invention relates to a method for selectively assembling and aligning nano-structures on a solid surface; and, more particularly, to a method for directly adsorbing the nano-structures on the solid surface with sliding the nano-structure from a slippery molecular layer to the solid surface after the solid surface is patterned into the slippery molecular layer. And the present invention can prevent the contamination of the nano-structure and the solid surface since the nano-structure is in direct contact with the solid surface. Further, the multi nano-structure manufactured in accordance with the present invention can be utilized as a sensor and is capable of adsorbing and cultivating bio-structures such as DNAs, proteins, cells or the like into desired shapes.

摘要翻译： 本发明涉及一种在固体表面上选择性地组装和对准纳米结构的方法; 更具体地说，涉及将固体表面图案化成光滑分子层之后，将纳米结构从光滑分子层滑动到固体表面的方法，直接将纳米结构吸附在固体表面上。 本发明可以防止纳米结构和固体表面的污染，因为纳米结构与固体表面直接接触。 此外，根据本发明制造的多纳米结构可以用作传感器，并且能够将生物结构如DNA，蛋白质，细胞等吸附和培养成所需的形状。

公开(公告)号：US20180114722A1

公开(公告)日：2018-04-26

申请号：US15464532

申请日：2017-03-21

申请人： Kwang Chul PARK ,  Ji Woon Im ,  Dai Hong Kim ,  ll Woo Kim ,  Hyun Seok Lim

发明人： Kwang Chul PARK ,  Ji Woon Im ,  Dai Hong Kim ,  ll Woo Kim ,  Hyun Seok Lim

IPC分类号： H01L21/768 ,  H01L21/02 ,  H01L21/311 ,  H01L21/28 ,  H01L27/1157 ,  H01L27/11582 ,  C23C16/48 ,  C23C16/50 ,  C23C16/54

CPC分类号： H01L21/76825 ,  C23C16/45523 ,  C23C16/482 ,  C23C16/50 ,  C23C16/54 ,  C23C16/56 ,  H01L21/02164 ,  H01L21/02348 ,  H01L21/28282 ,  H01L21/31111 ,  H01L21/76802 ,  H01L21/76877 ,  H01L27/1157 ,  H01L27/11582

摘要： A deposition apparatus includes a chamber, a plate in the chamber and configured support a substrate, a deposition unit configured to perform a deposition process in-situ in the chamber, and a UV annealing unit configured to perform a first ultraviolet (UV) and a second ultraviolet (UV) annealing process in-situ in the chamber. The deposition process may include sequentially depositing a first sacrificial layer, a first oxide layer, a second sacrificial layer and a second oxide layer on the substrate. The first UV annealing process may be performed on the first oxide layer after the first oxide layer is deposited. The second UV annealing process may be different from the first UV annealing process and may be performed on the second oxide layer after the second oxide layer is deposited.

公开(公告)号：US09865617B2

公开(公告)日：2018-01-09

申请号：US15402272

申请日：2017-01-10

申请人： Hauk Han ,  Ji Woon Im ,  Do Hyung Kim ,  Hyun Seok Lim

发明人： Hauk Han ,  Ji Woon Im ,  Do Hyung Kim ,  Hyun Seok Lim

IPC分类号： H01L23/528 ,  H01L29/36 ,  H01L27/11582 ,  H01L29/06 ,  H01L23/522 ,  H01L21/306

CPC分类号： H01L27/11582 ,  H01L21/30604 ,  H01L21/3115 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/1157 ,  H01L29/0649 ,  H01L29/36

摘要： A semiconductor device includes a first interlayer insulating layer and a second interlayer insulating layer, and a horizontal conductive pattern interposed between the first interlayer insulating layer and the second interlayer insulating layer. Vertical structures extend through the first interlayer insulating layer, the second interlayer insulating layer, and the horizontal conductive pattern. Each of the first interlayer insulating layer and the second interlayer insulating layer has regions of different impurity concentrations.

公开(公告)号：US20170330893A1

公开(公告)日：2017-11-16

申请号：US15402272

申请日：2017-01-10

申请人： HAUK HAN ,  JI WOON IM ,  DO HYUNG KIM ,  HYUN SEOK LIM

发明人： HAUK HAN ,  JI WOON IM ,  DO HYUNG KIM ,  HYUN SEOK LIM

IPC分类号： H01L27/11582 ,  H01L23/528 ,  H01L21/306 ,  H01L23/522 ,  H01L29/36 ,  H01L29/06

CPC分类号： H01L27/11582 ,  H01L21/30604 ,  H01L21/3115 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/1157 ,  H01L29/0649 ,  H01L29/36

摘要： A semiconductor device includes a first interlayer insulating layer and a second interlayer insulating layer, and a horizontal conductive pattern interposed between the first interlayer insulating layer and the second interlayer insulating layer. Vertical structures extend through the first interlayer insulating layer, the second interlayer insulating layer, and the horizontal conductive pattern. Each of the first interlayer insulating layer and the second interlayer insulating layer has regions of different impurity concentrations.

公开(公告)号：US09343475B2

公开(公告)日：2016-05-17

申请号：US14155842

申请日：2014-01-15

申请人： Kyung-Tae Jang ,  Sang-Hoon Lee ,  Ji-Youn Seo ,  Hyun-Yong Go ,  Koong-Hyun Nam ,  Ju-Wan Kim ,  Seung-Mok Shin ,  Myoung-Bum Lee ,  Ji-Woon Im ,  Tae-Jong Han

发明人： Kyung-Tae Jang ,  Sang-Hoon Lee ,  Ji-Youn Seo ,  Hyun-Yong Go ,  Koong-Hyun Nam ,  Ju-Wan Kim ,  Seung-Mok Shin ,  Myoung-Bum Lee ,  Ji-Woon Im ,  Tae-Jong Han

IPC分类号： H01L21/336 ,  H01L27/115 ,  H01L21/28

CPC分类号： H01L27/11582 ,  H01L21/28282 ,  H01L27/1157

摘要： In a method of a vertical memory device, insulation layers and sacrificial layers are alternately and repeatedly formed on a substrate. A hole is formed through the insulation layers and the sacrificial layers that expose a top surface of the substrate. Then, an interior portion of the hole may be enlarged. A semiconductor pattern is formed to partially fill the enlarged portion of the hole. A blocking layer, a charge storage layer and a tunnel insulation layer may be formed on a sidewall of the hole and the semiconductor pattern. Then, the tunnel insulation layer, the charge storage layer and the blocking layer are partially removed to expose a top surface of the semiconductor pattern. A channel is formed on the exposed top surface of the semiconductor pattern and the tunnel insulation layer. The sacrificial layers are replaced with gate electrodes.

摘要翻译： 在垂直存储器件的方法中，绝缘层和牺牲层在衬底上交替且重复地形成。 通过绝缘层和暴露衬底顶表面的牺牲层形成一个孔。 然后，可以扩大孔的内部。 半导体图案形成为部分地填充孔的扩大部分。 可以在孔和半导体图案的侧壁上形成阻挡层，电荷存储层和隧道绝缘层。 然后，部分去除隧道绝缘层，电荷存储层和阻挡层，以露出半导体图案的顶表面。 在半导体图案的暴露的顶表面和隧道绝缘层上形成沟道。 牺牲层被栅电极代替。

公开(公告)号：US20150200203A1

公开(公告)日：2015-07-16

申请号：US14155842

申请日：2014-01-15

申请人： Kyung-Tae Jang ,  Sang-Hoon Lee ,  Ji-Youn Seo ,  Hyun-Yong Go ,  Koong-Hyun Nam ,  Ju-Wan Kim ,  Seung-Mok Shin ,  Myoung-Bum Lee ,  Ji-Woon Im ,  Tae-Jong Han

发明人： Kyung-Tae Jang ,  Sang-Hoon Lee ,  Ji-Youn Seo ,  Hyun-Yong Go ,  Koong-Hyun Nam ,  Ju-Wan Kim ,  Seung-Mok Shin ,  Myoung-Bum Lee ,  Ji-Woon Im ,  Tae-Jong Han

IPC分类号： H01L27/115 ,  H01L29/66 ,  H01L29/788 ,  H01L21/28

CPC分类号： H01L27/11582 ,  H01L21/28282 ,  H01L27/1157

摘要： In a method of a vertical memory device, insulation layers and sacrificial layers are alternately and repeatedly formed on a substrate. A hole is formed through the insulation layers and the sacrificial layers that expose a top surface of the substrate. Then, an interior portion of the hole may be enlarged. A semiconductor pattern is formed to partially fill the enlarged portion of the hole. A blocking layer, a charge storage layer and a tunnel insulation layer may be formed on a sidewall of the hole and the semiconductor pattern. Then, the tunnel insulation layer, the charge storage layer and the blocking layer are partially removed to expose a top surface of the semiconductor pattern. A channel is formed on the exposed top surface of the semiconductor pattern and the tunnel insulation layer. The sacrificial layers are replaced with gate electrodes.

摘要翻译： 在垂直存储器件的方法中，绝缘层和牺牲层在衬底上交替且重复地形成。 通过绝缘层和暴露衬底顶表面的牺牲层形成一个孔。 然后，可以扩大孔的内部。 半导体图案形成为部分地填充孔的扩大部分。 可以在孔和半导体图案的侧壁上形成阻挡层，电荷存储层和隧道绝缘层。 然后，部分去除隧道绝缘层，电荷存储层和阻挡层，以露出半导体图案的顶表面。 在半导体图案的暴露的顶表面和隧道绝缘层上形成沟道。 牺牲层被栅电极代替。