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    Memory devices and methods of manufacturing the same
    1.
    发明授权
    Memory devices and methods of manufacturing the same 有权
    存储器件及其制造方法

    公开(公告)号：US09368646B2

    公开(公告)日：2016-06-14

    申请号：US14182325

    申请日：2014-02-18

    申请人： Jin-Gyun Kim ,  Jae-Young Ahn ,  Ki-Hyun Hwang

    发明人： Jin-Gyun Kim ,  Jae-Young Ahn ,  Ki-Hyun Hwang

    IPC分类号： H01L27/115 ,  H01L29/792 ,  H01L29/66

    CPC分类号： H01L29/7926 ,  H01L27/11582 ,  H01L29/66833

    摘要： A vertical memory device includes a channel array, a charge storage layer structure, multiple gate electrodes and a dummy pattern array. The channel array includes multiple channels, each of which is formed on a first region of a substrate and is formed to extend in a first direction substantially perpendicular to a top surface of the substrate. The charge storage layer structure includes a tunnel insulation layer pattern, a charge storage layer pattern and a blocking layer pattern, which are sequentially formed on a sidewall of each channel in the second direction substantially parallel to the top surface of the substrate. The gate electrodes arranged on a sidewall of the charge storage layer structure and spaced apart from each other in the first direction. The dummy pattern array includes multiple dummy patterns, each of which is formed on a second region adjacent the first region of the substrate and is formed to extend in the first direction.

    摘要翻译： 垂直存储器件包括沟道阵列，电荷存储层结构，多个栅电极和虚拟图案阵列。 通道阵列包括多个通道，每个通道形成在基板的第一区域上，并且形成为在基本上垂直于基板的顶表面的第一方向上延伸。 电荷存储层结构包括隧道绝缘层图案，电荷存储层图案和阻挡层图案，它们在基本上平行于基板的顶表面的第二方向上顺序地形成在每个沟道的侧壁上。 所述栅极布置在所述电荷存储层结构的侧壁上并且在所述第一方向上彼此间隔开。 虚拟图案阵列包括多个虚设图案，每个虚设图案形成在与基板的第一区域相邻的第二区域上，并且形成为沿第一方向延伸。

    Atomic Layer Deposition (ALD) Apparatus
    2.
    发明申请
    Atomic Layer Deposition (ALD) Apparatus 审中-公开
    原子层沉积（ALD）装置

    公开(公告)号：US20160122871A1

    公开(公告)日：2016-05-05

    申请号：US14743101

    申请日：2015-06-18

    申请人： Sang Hoon Lee ,  Jin Gyun Kim ,  Hyun Jin Shin ,  Han Vit Yang ,  Yong Seok Cho

    发明人： Sang Hoon Lee ,  Jin Gyun Kim ,  Hyun Jin Shin ,  Han Vit Yang ,  Yong Seok Cho

    IPC分类号： C23C16/455 ,  C23C16/50 ,  H01J37/32 ,  C23C16/52

    CPC分类号： H01J37/32449 ,  C23C16/045 ,  C23C16/452 ,  C23C16/45536 ,  H01J37/321 ,  H01L27/11582 ,  H01L29/40117

    摘要： An atomic layer deposition (ALD) apparatus includes a first process chamber in which a substrate is accommodated, a plasma generating unit provided on the outside of the first process chamber, a source gas supply unit provided on an upper portion of the plasma generating unit, and configured to supply a plurality of source gases, a purge gas supply unit configured to supply a purge gas to the first process chamber, and a gas control unit configured to control the supply of the source gases and the purge gas, wherein the plasma generating unit includes a second process chamber providing a space in which plasma is generated and a plasma antenna inducing a magnetic field in the second process chamber, and the source gases are supplied to the first process chamber through the plasma generating unit.

    摘要翻译： 原子层沉积（ALD）装置包括容纳基板的第一处理室，设置在第一处理室外侧的等离子体产生单元，设置在等离子体产生单元的上部的源气体供应单元， 并且被配置为提供多个源气体;净化气体供应单元，被配置为向第一处理室供应净化气体;气体控制单元，被配置为控制源气体和净化气体的供应，其中等离子体产生 单元包括提供产生等离子体的空间的第二处理室和在第二处理室中产生磁场的等离子体天线，并且源气体通过等离子体产生单元供应到第一处理室。

    MEMORY DEVICE
    3.
    发明申请
    MEMORY DEVICE 有权
    内存设备

    公开(公告)号：US20150372000A1

    公开(公告)日：2015-12-24

    申请号：US14593077

    申请日：2015-01-09

    申请人： Jung Geun JEE ,  Dong Kyum KIM ,  Jin Gyun KIM ,  Ki Hyun HWANG

    发明人： Jung Geun JEE ,  Dong Kyum KIM ,  Jin Gyun KIM ,  Ki Hyun HWANG

    IPC分类号： H01L27/115 ,  H01L29/16 ,  H01L29/792 ,  H01L29/788

    CPC分类号： H01L27/11573 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11568 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11582 ,  H01L29/16 ,  H01L29/788 ,  H01L29/792

    摘要： There is provided a peripheral circuit region including a plurality of circuit elements disposed on a first substrate; and a cell region including at least one channel region extending from an upper surface of a second substrate disposed on the first substrate in a direction perpendicular to the upper surface of the second substrate, and a plurality of gate electrode layers and a plurality of insulating layers stacked on the second substrate to be adjacent to the at least one channel region, wherein at least a portion of the first substrate contacts the second substrate, and the first substrate and the second substrate provide a single substrate.

    摘要翻译： 提供了包括设置在第一基板上的多个电路元件的外围电路区域; 以及单元区域，包括至少一个沟道区域，所述沟道区域从垂直于所述第二衬底的上表面的方向从设置在所述第一衬底上的第二衬底的上表面延伸，以及多个栅电极层和多个绝缘层 堆叠在所述第二衬底上以邻近所述至少一个沟道区域，其中所述第一衬底的至少一部分接触所述第二衬底，并且所述第一衬底和所述第二衬底提供单个衬底。

    Semiconductor device including a first core pattern under a second core pattern
    4.
    发明授权
    Semiconductor device including a first core pattern under a second core pattern 有权
    半导体器件包括在第二芯图案下的第一芯图案

    公开(公告)号：US09129857B2

    公开(公告)日：2015-09-08

    申请号：US13560022

    申请日：2012-07-27

    申请人： Bi-O Kim ,  Byong-Ju Kim ,  Jung-Geun Jee ,  Jin-Gyun Kim ,  Jae-Young Ahn ,  Ki-Hyun Hwang

    发明人： Bi-O Kim ,  Byong-Ju Kim ,  Jung-Geun Jee ,  Jin-Gyun Kim ,  Jae-Young Ahn ,  Ki-Hyun Hwang

    IPC分类号： H01L29/792 ,  H01L27/115 ,  H01L21/336

    CPC分类号： H01L27/1157 ,  H01L27/11582 ,  H01L29/105

    摘要： According to example embodiments, a semiconductor device includes horizontal patterns stacked on a substrate. The horizontal patterns define an opening through the horizontal patterns. A first core pattern is in the opening. A second core pattern is in the opening on the first core pattern. A first active pattern is between the first core pattern and the horizontal patterns. A second active pattern containing a first element is between the second core pattern and the horizontal patterns. The second active pattern contains the first element at a higher concentration than a concentration of the first element in the second core pattern.

    摘要翻译： 根据示例性实施例，半导体器件包括堆叠在衬底上的水平图案。 水平图案通过水平图案定义开口。 第一个核心模式是在开幕。 第一个核心模式是第一个核心模式的开放。 第一活动模式在第一芯图案和水平图案之间。 包含第一元件的第二活动图案位于第二芯图案和水平图案之间。 第二活性图案含有比第二芯图案中的第一元素的浓度高的浓度的第一元素。

    Three dimensional semiconductor memory device and method of fabricating the same
    5.
    发明授权
    Three dimensional semiconductor memory device and method of fabricating the same 有权
    三维半导体存储器件及其制造方法

    公开(公告)号：US08815676B2

    公开(公告)日：2014-08-26

    申请号：US13671948

    申请日：2012-11-08

    申请人： Sang-Ryol Yang ,  Yoo-Chul Kong ,  Jung-Ho Kim ,  Jin-Gyun Kim ,  Jae-Jin Shin ,  Ji-Hoon Choi

    发明人： Sang-Ryol Yang ,  Yoo-Chul Kong ,  Jung-Ho Kim ,  Jin-Gyun Kim ,  Jae-Jin Shin ,  Ji-Hoon Choi

    IPC分类号： H01L21/00

    CPC分类号： H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157

    摘要： Methods of forming vertical nonvolatile memory devices may include forming an electrically insulating layer, which includes a composite of a sacrificial layer sandwiched between first and second mold layers. An opening extends through the electrically insulating layer and exposes inner sidewalls of the first and second mold layers and the sacrificial layer. A sidewall of the opening may be lined with an electrically insulating protective layer and a first semiconductor layer may be formed on an inner sidewall of the electrically insulating protective layer within the opening. At least a portion of the sacrificial layer may then be selectively etched from between the first and second mold layers to thereby define a lateral recess therein, which exposes an outer sidewall of the electrically insulating protective layer.

    摘要翻译： 形成垂直非易失性存储器件的方法可以包括形成电绝缘层，其包括夹在第一和第二模具层之间的牺牲层的复合材料。 开口延伸穿过电绝缘层并暴露第一和第二模具层和牺牲层的内侧壁。 开口的侧壁可以衬有电绝缘保护层，并且可以在开口内的电绝缘保护层的内侧壁上形成第一半导体层。 然后可以从第一和第二模具层之间选择性地蚀刻牺牲层的至少一部分，从而在其中限定其中暴露电绝缘保护层的外侧壁的横向凹部。

    Vertical semiconductor devices
    6.
    发明授权
    Vertical semiconductor devices 有权
    垂直半导体器件

    公开(公告)号：US08564046B2

    公开(公告)日：2013-10-22

    申请号：US13104377

    申请日：2011-05-10

    申请人： Jin-Gyun Kim ,  Myoung-Bum Lee

    发明人： Jin-Gyun Kim ,  Myoung-Bum Lee

    IPC分类号： H01L29/792

    CPC分类号： H01L27/11578 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/7926

    摘要： A vertical semiconductor device and a method of making a vertical semiconductor device include a first semiconductor pattern formed on a substrate and a first gate structure formed on a sidewall of the first semiconductor pattern. A second semiconductor pattern is formed on the first semiconductor pattern. A plurality of insulating interlayer patterns is formed on sidewalls of the second semiconductor pattern. The insulating interlayer patterns are spaced apart from each other to define grooves between the insulating interlayer patterns. The plurality of second gate structures is disposed in the grooves, respectively.

    摘要翻译： 垂直半导体器件和制造垂直半导体器件的方法包括形成在衬底上的第一半导体图案和形成在第一半导体图案的侧壁上的第一栅极结构。 在第一半导体图案上形成第二半导体图案。 在第二半导体图案的侧壁上形成多个绝缘层间图案。 绝缘层间图案彼此间隔开以在绝缘层间图案之间限定凹槽。 多个第二栅极结构分别设置在沟槽中。

    Vertical memory devices including indium and/or gallium channel doping
    7.
    发明授权
    Vertical memory devices including indium and/or gallium channel doping 有权
    垂直存储器件包括铟和/或镓通道掺杂

    公开(公告)号：US08497555B2

    公开(公告)日：2013-07-30

    申请号：US13298728

    申请日：2011-11-17

    申请人： Jin-Gyun Kim ,  Ki-Hyun Hwang ,  Sung-Hae Lee ,  Ji-Hoon Choi

    发明人： Jin-Gyun Kim ,  Ki-Hyun Hwang ,  Sung-Hae Lee ,  Ji-Hoon Choi

    IPC分类号： H01L29/792 ,  G11C11/40

    CPC分类号： H01L29/7926 ,  H01L27/11582 ,  H01L29/1041 ,  H01L29/167 ,  H01L29/7923

    摘要： A vertical memory device may include a substrate, a first selection line on the substrate, a plurality of word lines on the first selection line, a second selection line on the plurality of word lines, and a semiconductor channel. The first selection line may be between the plurality of word lines and the substrate, and the plurality of word lines may be between the first and second selection lines. Moreover, the first and second selection lines and the plurality of word lines may be spaced apart in a direction perpendicular with respect to a surface of the substrate. The semiconductor channel may extend away from the surface of the substrate adjacent sidewalls of the first and second selection lines and the plurality of word lines. In addition, portions of the semiconductor channel adjacent the second selection line may be doped with indium and/or gallium. Related methods are also discussed.

    摘要翻译： 垂直存储器件可以包括衬底，衬底上的第一选择线，第一选择线上的多个字线，多个字线上的第二选择线，以及半导体沟道。 第一选择线可以在多个字线和衬底之间，并且多个字线可以在第一和第二选择线之间。 此外，第一选择线和第二选择线和多个字线可以在与衬底的表面垂直的方向上间隔开。 半导体通道可以延伸离开衬底的与第一和第二选择线和多个字线的侧壁相邻的表面。 此外，与第二选择线相邻的半导体通道的部分可以掺杂铟和/或镓。 还讨论了相关方法。

    METHOD OF MANUFACTURING VERTICAL SEMICONDUCTOR DEVICES
    9.
    发明申请
    METHOD OF MANUFACTURING VERTICAL SEMICONDUCTOR DEVICES 审中-公开
    制造垂直半导体器件的方法

    公开(公告)号：US20110306195A1

    公开(公告)日：2011-12-15

    申请号：US13099485

    申请日：2011-05-03

    申请人： Jin-Gyun Kim ,  Bo-Young Lee ,  Ki-Hyun Hwang ,  Eunkee Hong ,  Jong-Wan Choi

    发明人： Jin-Gyun Kim ,  Bo-Young Lee ,  Ki-Hyun Hwang ,  Eunkee Hong ,  Jong-Wan Choi

    IPC分类号： H01L21/28

    CPC分类号： H01L27/11578 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/7926

    摘要： In a vertical semiconductor device and a method of manufacturing a vertical semiconductor device, sacrificial layers and insulating interlayers are repeatedly and alternately stacked on a substrate. The sacrificial layers include boron (B) and nitrogen (N) and have an etching selectivity with respect to the insulating interlayers. Semiconductor patterns are formed on the substrate through the sacrificial layers and the insulating interlayers. The sacrificial layers and the insulating interlayers are at least partially removed between the semiconductor patterns to form sacrificial layer patterns and insulating interlayer patterns on sidewalls of the semiconductor patterns. The sacrificial layer patterns are removed to form grooves between the insulating interlayer patterns. The grooves expose portions of the sidewalls of the semiconductor patterns. A gate structure is formed in each of the grooves.

    摘要翻译： 在垂直半导体器件和制造垂直半导体器件的方法中，牺牲层和绝缘夹层重叠交替堆叠在衬底上。 牺牲层包括硼（B）和氮（N），并且相对于绝缘夹层具有蚀刻选择性。 通过牺牲层和绝缘夹层在衬底上形成半导体图案。 在半导体图案之间至少部分去除牺牲层和绝缘夹层，以在半导体图案的侧壁上形成牺牲层图案和绝缘层间图案。 去除牺牲层图案以在绝缘层间图案之间形成凹槽。 凹槽暴露半导体图案的侧壁的部分。 在每个槽中形成栅极结构。