公开(公告)号：US07553758B2

公开(公告)日：2009-06-30

申请号：US11532719

申请日：2006-09-18

申请人： Wan-jae Park ,  Hyung-yoon Choi ,  Yi-hsiung Lin ,  Tong Qing Chen

发明人： Wan-jae Park ,  Hyung-yoon Choi ,  Yi-hsiung Lin ,  Tong Qing Chen

IPC分类号： H01L21/4763

CPC分类号： H01L21/3146 ,  H01L21/02115 ,  H01L21/0212 ,  H01L21/02167 ,  H01L21/02271 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/31155 ,  H01L21/76807 ,  H01L21/76825 ,  H01L21/76829 ,  H01L2221/1063 ,  Y10S438/924

摘要： Method of Fabricating Interconnections of a Microelectronic Device Using a Dual Damascene Process. A method of fabricating interconnections of a microelectronic device includes preparing a semiconductor substrate comprising a lower dielectric layer and a lower interconnection, forming an etch stopper layer and an interlayer dielectric layer on the semiconductor substrate, forming a via hole in the interlayer dielectric layer so that the etch stopper layer is exposed through the via hole, performing carbon doping on the etch stopper layer, performing trench etching to form a trench in the interlayer dielectric layer so that the trench overlaps part of the via hole, removing the carbon-doped etch stopper layer, and filling the via hole and the trench with a conductive material to form an upper interconnection.

摘要翻译： 使用双镶嵌工艺制造微电子器件互连的方法。 制造微电子器件的互连的方法包括制备包括下电介质层和下互连的半导体衬底，在半导体衬底上形成蚀刻停止层和层间电介质层，在层间电介质层中形成通孔，使得 蚀刻阻挡层通过通孔露出，在蚀刻停止层上进行碳掺杂，进行沟槽蚀刻以在层间电介质层中形成沟槽，使得沟槽与通孔的一部分重叠，去除碳掺杂的蚀刻阻挡层 层，并且用导电材料填充通孔和沟槽以形成上互连。

公开(公告)号：US20080070409A1

公开(公告)日：2008-03-20

申请号：US11532719

申请日：2006-09-18

申请人： Wan-jae Park ,  Hyung-yoon Choi ,  Yi-hsiung Lin ,  Tong Qing Chen

发明人： Wan-jae Park ,  Hyung-yoon Choi ,  Yi-hsiung Lin ,  Tong Qing Chen

IPC分类号： H01L21/44

CPC分类号： H01L21/3146 ,  H01L21/02115 ,  H01L21/0212 ,  H01L21/02167 ,  H01L21/02271 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/31155 ,  H01L21/76807 ,  H01L21/76825 ,  H01L21/76829 ,  H01L2221/1063 ,  Y10S438/924

摘要： Method of Fabricating Interconnections of a Microelectronic Device Using a Dual Damascene Process. A method of fabricating interconnections of a microelectronic device includes preparing a semiconductor substrate comprising a lower dielectric layer and a lower interconnection, forming an etch stopper layer and an interlayer dielectric layer on the semiconductor substrate, forming a via hole in the interlayer dielectric layer so that the etch stopper layer is exposed through the via hole, performing carbon doping on the etch stopper layer, performing trench etching to form a trench in the interlayer dielectric layer so that the trench overlaps part of the via hole, removing the carbon-doped etch stopper layer, and filling the via hole and the trench with a conductive material to form an upper interconnection.

摘要翻译： 使用双镶嵌工艺制造微电子器件互连的方法。 制造微电子器件的互连的方法包括制备包括下电介质层和下互连的半导体衬底，在半导体衬底上形成蚀刻停止层和层间电介质层，在层间电介质层中形成通孔，使得 蚀刻阻挡层通过通孔露出，在蚀刻停止层上进行碳掺杂，进行沟槽蚀刻以在层间电介质层中形成沟槽，使得沟槽与通孔的一部分重叠，去除碳掺杂的蚀刻阻挡层 层，并且用导电材料填充通孔和沟槽以形成上互连。

公开(公告)号：US20090146181A1

公开(公告)日：2009-06-11

申请号：US11952939

申请日：2007-12-07

申请人： Chung Woh Lai ,  Oleg Gluschenkov ,  Henry K. Utomo ,  Lee Wee Teo ,  Jin Ping Liu ,  Anita Madan ,  Rainer Loesing ,  Jin-Ping Han ,  Hyung-Yoon Choi

发明人： Chung Woh Lai ,  Oleg Gluschenkov ,  Henry K. Utomo ,  Lee Wee Teo ,  Jin Ping Liu ,  Anita Madan ,  Rainer Loesing ,  Jin-Ping Han ,  Hyung-Yoon Choi

IPC分类号： H01L29/778 ,  H01L21/336 ,  H01L29/78

CPC分类号： H01L21/823814 ,  H01L21/823807 ,  H01L27/1203 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848

摘要： An integrated circuit system that includes: providing a PFET device including a doped epitaxial layer; and forming a source/drain extension by employing an energy source to diffuse a dopant from the doped epitaxial layer.

摘要翻译： 一种集成电路系统，包括：提供包括掺杂外延层的PFET器件; 以及通过使用能量源从掺杂的外延层扩散掺杂剂形成源极/漏极扩展。

公开(公告)号：US20090050972A1

公开(公告)日：2009-02-26

申请号：US11841516

申请日：2007-08-20

申请人： Richard Lindsay ,  Shyue Seng Tan ,  Joo-Chan Kim ,  Jun Jung Kim ,  Hyung-Yoon Choi ,  Chung Woh Lai ,  Johnny Widodo

发明人： Richard Lindsay ,  Shyue Seng Tan ,  Joo-Chan Kim ,  Jun Jung Kim ,  Hyung-Yoon Choi ,  Chung Woh Lai ,  Johnny Widodo

IPC分类号： H01L21/768 ,  H01L23/48 ,  H01L21/336 ,  H01L29/78

CPC分类号： H01L29/7843 ,  H01L21/28518 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/823807 ,  H01L21/823871 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： A method of making a semiconductor device is disclosed. A semiconductor body, a gate electrode and source/drain regions are provided. A liner is provided that covers the gate electrode and the source/drain regions. Silicide regions are formed on the semiconductor device by etching a contact hole through the liner.

摘要翻译： 公开了制造半导体器件的方法。 提供半导体本体，栅极电极和源极/漏极区域。 提供覆盖栅极电极和源极/漏极区域的衬垫。 通过蚀刻通过衬套的接触孔，在半导体器件上形成硅化物区域。