Method for welding hollow structure
    1.
    发明授权
    Method for welding hollow structure 有权
    中空结构焊接方法

    公开(公告)号:US08590767B2

    公开(公告)日:2013-11-26

    申请号:US13164867

    申请日:2011-06-21

    CPC classification number: B23K20/126

    Abstract: In the method for welding a hollow structure of the present invention, a rib is placed between a first joining member and a second joining member, and friction stir welding and fixing a place where the rib is placed between the first and the second joining member are conducted. Thus, friction stir welding is accomplished without changing the shape of an extrusion part or partly changing the shape of the extrusion part with insertion of a simply shaped rib.

    Abstract translation: 在本发明的中空结构焊接方法中,在第一接合构件和第二接合构件之间设置有肋,并且摩擦搅拌焊接和固定肋放置在第一和第二接合构件之间的位置是 进行。 因此,在不改变挤压部件的形状的情况下实现摩擦搅拌焊接,或者通过插入简单成型的肋部来部分地改变挤压部件的形状。

    MULTI-LINKAGE AND MULTI-TREE STRUCTURE SYSTEM AND METHOD OF CONTROLLING THE SAME
    2.
    发明申请
    MULTI-LINKAGE AND MULTI-TREE STRUCTURE SYSTEM AND METHOD OF CONTROLLING THE SAME 审中-公开
    多连接和多树结构体系及其控制方法

    公开(公告)号:US20120245711A1

    公开(公告)日:2012-09-27

    申请号:US13349159

    申请日:2012-01-12

    Applicant: In-gyu PARK

    Inventor: In-gyu PARK

    Abstract: A multi-linkage and multi-tree structure system includes: a base body including a sensor for detecting movement of the base body; at least one link body which is connected to the base body via at least one first joint and moves relative to the base body with respect to at least one axis, wherein movement of the at least one link body is independently controlled based on the movement of the base body detected by the sensor, and wherein each of the at least one link body comprises one or more links that are connected to one another via at least one second joint, and at least one link in each of the at least one link body is controlled by the controller to orient toward a set direction with respect to the movement of the base body.

    Abstract translation: 多连杆多树结构体系包括:基体,包括用于检测基体的运动的传感器; 至少一个连接体,其经由至少一个第一接头连接到所述基体,并且相对于至少一个轴线相对于所述基体移动,其中所述至少一个连接体的运动基于 所述基体由所述传感器检测到,并且其中所述至少一个连接体中的每一个包括经由至少一个第二接头彼此连接的一个或多个连杆,并且所述至少一个连杆体中的至少一个连杆体中的至少一个连杆 由控制器控制以相对于基体的运动朝向设定方向定向。

    Power gating circuit, system on chip circuit including the same and power gating method
    3.
    发明授权
    Power gating circuit, system on chip circuit including the same and power gating method 有权
    电源门控电路,片上电路包括相同的电源门控方式

    公开(公告)号:US07782701B2

    公开(公告)日:2010-08-24

    申请号:US11846677

    申请日:2007-08-29

    CPC classification number: G11C5/14 H03K19/0016

    Abstract: A power gating circuit of a memory device includes a power gating unit and a control unit. The power gating unit includes first, second, and third power gating transistors connected in parallel between a power supply voltage and an internal power supply voltage bus of the memory device. The three power gating transistors are sequentially turned ON. The second and third power gating transistors turn ON sequentially in response to the increasing voltage level of the bus. The timing points when the second and third power gating transistors are sequentially turned ON is based upon detecting the gradually increasing the voltage level of the internal power supply voltage. The size of the first power gating transistor may be smaller than the size of the second power gating transistor, and the size of the second power gating transistor may be smaller than the size of the third power gating transistor.

    Abstract translation: 存储器件的电源门控电路包括电源门控单元和控制单元。 电源门控单元包括并联连接在存储器件的电源电压和内部电源电压总线之间的第一,第二和第三电源门控晶体管。 三个电源门控晶体管依次导通。 第二和第三电源门控晶体管响应于总线的电压增加而依次接通。 当第二和第三功率选通晶体管依次导通时的定时点是基于检测到逐渐增加内部电源电压的电压电平。 第一功率门控晶体管的尺寸可以小于第二功率门控晶体管的尺寸,并且第二功率门控晶体管的尺寸可以小于第三功率门控晶体管的尺寸。

    METHOD FOR WELDING HOLLOW STRUCTURE
    5.
    发明申请
    METHOD FOR WELDING HOLLOW STRUCTURE 有权
    焊接中空结构的方法

    公开(公告)号:US20120325894A1

    公开(公告)日:2012-12-27

    申请号:US13164867

    申请日:2011-06-21

    CPC classification number: B23K20/126

    Abstract: In the method for welding a hollow structure of the present invention, a rib is placed between a first joining member and a second joining member, and friction stir welding and fixing a place where the rib is placed between the first and the second joining member are conducted. Thus, friction stir welding is accomplished without changing the shape of an extrusion part or partly changing the shape of the extrusion part with insertion of a simply shaped rib.

    Abstract translation: 在本发明的中空结构焊接方法中,在第一接合构件和第二接合构件之间设置有肋,并且摩擦搅拌焊接和固定肋放置在第一和第二接合构件之间的位置是 进行。 因此,在不改变挤压部件的形状的情况下实现摩擦搅拌焊接,或者通过插入简单成型的肋部来部分地改变挤压部件的形状。

    Semiconductor memory device
    6.
    发明授权
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号:US06947343B2

    公开(公告)日:2005-09-20

    申请号:US10780925

    申请日:2004-02-19

    Applicant: In-Gyu Park

    Inventor: In-Gyu Park

    Abstract: Each memory block of a memory device a plurality of memory cells connected to a plurality of bit line pairs, a column selecting circuit, and a pre-charge and write control circuit. The column selecting circuit includes a plurality of CMOS transmission gates, each CMOS transmission gate including an NMOS transistor connected between one bit line of a bit line pair and a sense bit line of a sense bit line pair, and a PMOS transistor connected between the one bit line and one of the write bit lines of a write bit line pair. During a write operation, only the NMOS transistor of a selected one of the CMOS transmission gates is turned on, and the PMOS transistor of the selected CMOS transmission gate and the PMOS and NMOS transistors of all of the CMOS transmission gates except the selected one are all turned off.

    Abstract translation: 存储器件的每个存储器块连接到多个位线对的多个存储器单元,列选择电路和预充电和写入控制电路。 列选择电路包括多个CMOS传输门,每个CMOS传输门包括连接在位线对的一个位线和感测位线对的感测位线之间的NMOS晶体管,以及连接在一个 位线和写位线对的写位线之一。 在写操作期间,仅CMOS选择的一个CMOS传输门的NMOS晶体管导通,所选择的CMOS传输门的PMOS晶体管和所有CMOS传输门的PMOS晶体管和NMOS晶体管除了选定的CMOS传输门之外 全部关闭

    Read only memory devices with independently precharged virtual ground and bit lines
    7.
    发明授权
    Read only memory devices with independently precharged virtual ground and bit lines 有权
    只读存储器件,具有独立预充电的虚拟接地和位线

    公开(公告)号:US07042750B2

    公开(公告)日:2006-05-09

    申请号:US10910669

    申请日:2004-08-03

    CPC classification number: G11C17/126 G11C7/12

    Abstract: Read only memory(ROM) integrated circuit devices include a ROM cell block. A plurality of virtual ground lines and bit lines are coupled to the ROM cell block. A precharge circuit, including a virtual ground line precharge controller, virtual ground line precharging unit, bit line precharge controller and bit line precharging unit, independently controls timing of precharging the virtual ground lines and the bit lines. The precharge circuit may be configured to deactivate precharging of the virtual ground lines before deactivating precharging of the bit lines. Precharging of the virtual ground lines may be deactivated substantially concurrently with activation of discharging of the virtual ground lines.

    Abstract translation: 只读存储器(ROM)集成电路器件包括ROM单元块。 多个虚拟接地线和位线耦合到ROM单元块。 包括虚拟地线预充电控制器,虚拟地线预充电单元,位线预充电控制器和位线预充电单元的预充电电路独立地控制对虚拟接地线和位线进行预充电的定时。 预充电电路可以被配置为在停用位线的预充电之前停用虚拟接地线的预充电。 虚拟接地线的预充电可以与虚拟接地线的放电的激活基本同时被去激活。

    Read only memory devices with independently precharged virtual ground and bit lines and methods for operating the same

    公开(公告)号:US06801446B2

    公开(公告)日:2004-10-05

    申请号:US10406476

    申请日:2003-04-03

    CPC classification number: G11C7/12

    Abstract: Read only memory (ROM) integrated circuit devices include one or more storage cells. A virtual ground line and a bit line are coupled to the storage cell. A precharge circuit independently controls timing of precharging of the virtual ground line and the bit line. The precharge circuit may be configured to deactivate precharging of the virtual ground line before deactivating precharging of the bit line. Precharging of the virtual ground line may be deactivated substantially concurrently with activation of discharging of the virtual ground line. Methods of operating such ROM integrated circuit devices are also provided.

    Electrodes of electron gun
    9.
    发明授权
    Electrodes of electron gun 失效
    电子枪电极

    公开(公告)号:US06586869B1

    公开(公告)日:2003-07-01

    申请号:US09714967

    申请日:2000-11-20

    CPC classification number: H01J29/62 H01J29/503 H01J2229/481 H01J2229/4872

    Abstract: Electrodes of an electron gun including a pair of first and second outer rim electrode members installed to face one another and where large diameter electron beam apertures through which three electron beams pass are respectively formed, and first and second inner electrode member installed in the outer rim electrode members, respectively, and where three small diameter electron beam apertures are formed to have an in-line shape. In the above electrodes, a burring portion is formed at the edge of the large diameter electron beam aperture of the first outer rim electrode member at one side of the outer rim electrode members facing each other, and the vertical diameter of the electron beam aperture formed in the middle of the small diameter electron beam apertures formed at the first inner electrode is formed to be greater than those of the two other small diameter electron beam apertures.

    Abstract translation: 电子枪的电极包括一对第一和第二外缘电极部件,第一外缘电极部件和第二外缘电极部件被安装成彼此面对并且分别形成有三个电子束通过的大直径的电子束孔径;以及第一和第二内部电极部件,安装在外部边缘 电极构件,并且其中三个小直径电子束孔形成为具有直列形状。 在上述电极中,在第一外缘电极部件的大直径电子束孔的边缘处,在外缘电极部件的彼此面对的一侧形成有翻边部分,形成电子束孔的垂直直径 在形成在第一内部电极处的小直径电子束孔的中间形成为大于另外两个小直径电子束孔的那些。

    Negative voltage generator and semiconductor memory device
    10.
    发明授权
    Negative voltage generator and semiconductor memory device 有权
    负电压发生器和半导体存储器件

    公开(公告)号:US08934313B2

    公开(公告)日:2015-01-13

    申请号:US13358121

    申请日:2012-01-25

    CPC classification number: G11C11/419 G11C5/145 G11C7/12

    Abstract: A negative voltage generator includes a variable-capacitance negative voltage generating unit, a switching unit and a positive voltage applying unit. The negative voltage generating unit includes a plurality of coupling capacitors for varying the capacitance in which the negative voltage is charged. The negative voltage generating unit selects at least one coupling capacitor of the plurality of coupling capacitors according to the number of rows (size) of a memory bank to which data is written, and charges the at least one selected coupling capacitor to a negative voltage. The switching unit selects one bitline of a bitline pair having complementary first and second bitlines in response to the data, and connects the at least one selected coupling capacitor to the selected bitline. The positive voltage applying unit applies a positive (high) voltage to an other bitline of the bitline pair.

    Abstract translation: 负电压发生器包括可变电容负电压产生单元,开关单元和正电压施加单元。 负电压产生单元包括用于改变负电压被充电的电容的多个耦合电容器。 负电压产生单元根据写入数据的存储体组的行数(大小)选择多个耦合电容器中的至少一个耦合电容器,并将至少一个所选择的耦合电容器充电至负电压。 切换单元响应于数据选择具有互补的第一和第二位线的位线对的一个位线,并且将至少一个选择的耦合电容器连接到所选择的位线。 正电压施加单元将正(高)电压施加到位线对的另一位线。

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