Abstract:
In the method for welding a hollow structure of the present invention, a rib is placed between a first joining member and a second joining member, and friction stir welding and fixing a place where the rib is placed between the first and the second joining member are conducted. Thus, friction stir welding is accomplished without changing the shape of an extrusion part or partly changing the shape of the extrusion part with insertion of a simply shaped rib.
Abstract:
A multi-linkage and multi-tree structure system includes: a base body including a sensor for detecting movement of the base body; at least one link body which is connected to the base body via at least one first joint and moves relative to the base body with respect to at least one axis, wherein movement of the at least one link body is independently controlled based on the movement of the base body detected by the sensor, and wherein each of the at least one link body comprises one or more links that are connected to one another via at least one second joint, and at least one link in each of the at least one link body is controlled by the controller to orient toward a set direction with respect to the movement of the base body.
Abstract:
A power gating circuit of a memory device includes a power gating unit and a control unit. The power gating unit includes first, second, and third power gating transistors connected in parallel between a power supply voltage and an internal power supply voltage bus of the memory device. The three power gating transistors are sequentially turned ON. The second and third power gating transistors turn ON sequentially in response to the increasing voltage level of the bus. The timing points when the second and third power gating transistors are sequentially turned ON is based upon detecting the gradually increasing the voltage level of the internal power supply voltage. The size of the first power gating transistor may be smaller than the size of the second power gating transistor, and the size of the second power gating transistor may be smaller than the size of the third power gating transistor.
Abstract:
A cross-linked polyethylene composition for a power cable insulator including (A) 100 parts by weight of a polyethylene base resin, (B) 0.1 to 0.6 parts by weight of a hindered phenol-based antioxidant, (C) 1 to 4 parts by weight of a crosslinking agent, (D) 0.2 to 1.0 parts by weight of magnesium oxide and (E) 0.1 to 1.0 parts by weight of a scorch inhibitor, which advantageously exhibits superior resistance to water tree generated when a power cable insulator is exposed to outside water and electric field, and superior electrical insulation characteristics.
Abstract:
In the method for welding a hollow structure of the present invention, a rib is placed between a first joining member and a second joining member, and friction stir welding and fixing a place where the rib is placed between the first and the second joining member are conducted. Thus, friction stir welding is accomplished without changing the shape of an extrusion part or partly changing the shape of the extrusion part with insertion of a simply shaped rib.
Abstract:
Each memory block of a memory device a plurality of memory cells connected to a plurality of bit line pairs, a column selecting circuit, and a pre-charge and write control circuit. The column selecting circuit includes a plurality of CMOS transmission gates, each CMOS transmission gate including an NMOS transistor connected between one bit line of a bit line pair and a sense bit line of a sense bit line pair, and a PMOS transistor connected between the one bit line and one of the write bit lines of a write bit line pair. During a write operation, only the NMOS transistor of a selected one of the CMOS transmission gates is turned on, and the PMOS transistor of the selected CMOS transmission gate and the PMOS and NMOS transistors of all of the CMOS transmission gates except the selected one are all turned off.
Abstract:
Read only memory(ROM) integrated circuit devices include a ROM cell block. A plurality of virtual ground lines and bit lines are coupled to the ROM cell block. A precharge circuit, including a virtual ground line precharge controller, virtual ground line precharging unit, bit line precharge controller and bit line precharging unit, independently controls timing of precharging the virtual ground lines and the bit lines. The precharge circuit may be configured to deactivate precharging of the virtual ground lines before deactivating precharging of the bit lines. Precharging of the virtual ground lines may be deactivated substantially concurrently with activation of discharging of the virtual ground lines.
Abstract:
Read only memory (ROM) integrated circuit devices include one or more storage cells. A virtual ground line and a bit line are coupled to the storage cell. A precharge circuit independently controls timing of precharging of the virtual ground line and the bit line. The precharge circuit may be configured to deactivate precharging of the virtual ground line before deactivating precharging of the bit line. Precharging of the virtual ground line may be deactivated substantially concurrently with activation of discharging of the virtual ground line. Methods of operating such ROM integrated circuit devices are also provided.
Abstract:
Electrodes of an electron gun including a pair of first and second outer rim electrode members installed to face one another and where large diameter electron beam apertures through which three electron beams pass are respectively formed, and first and second inner electrode member installed in the outer rim electrode members, respectively, and where three small diameter electron beam apertures are formed to have an in-line shape. In the above electrodes, a burring portion is formed at the edge of the large diameter electron beam aperture of the first outer rim electrode member at one side of the outer rim electrode members facing each other, and the vertical diameter of the electron beam aperture formed in the middle of the small diameter electron beam apertures formed at the first inner electrode is formed to be greater than those of the two other small diameter electron beam apertures.
Abstract:
A negative voltage generator includes a variable-capacitance negative voltage generating unit, a switching unit and a positive voltage applying unit. The negative voltage generating unit includes a plurality of coupling capacitors for varying the capacitance in which the negative voltage is charged. The negative voltage generating unit selects at least one coupling capacitor of the plurality of coupling capacitors according to the number of rows (size) of a memory bank to which data is written, and charges the at least one selected coupling capacitor to a negative voltage. The switching unit selects one bitline of a bitline pair having complementary first and second bitlines in response to the data, and connects the at least one selected coupling capacitor to the selected bitline. The positive voltage applying unit applies a positive (high) voltage to an other bitline of the bitline pair.