公开(公告)号：US5345194A

公开(公告)日：1994-09-06

申请号：US914209

申请日：1992-07-14

Applicant: Isamu Nagasako

Inventor： Isamu Nagasako

IPC: H01L27/06 ,  H01L21/338 ,  H01L21/8232 ,  H01L29/423 ,  H01L29/812 ,  H03B5/18 ,  H03B7/14 ,  H03D9/06 ,  H04B1/26

CPC classification number: H01L29/42316 ,  H03B5/1852 ,  H03D9/0675 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/12032 ,  H03B7/14

Abstract: A FET comprising two or more gate pads or terminals, and a reflection type oscillator including the above-mentioned FET. In this oscillator, a dielectric resonator is connected through a coupling line to the first gate pad of the FET and an output terminal is connected to the second pad. When the drain pad of the FET is connected to ground, and a suitable value of capacitive reactance is added to the source pad, then a negative resistance -R appears on the first gate pad, and thus oscillation occurs at a resonance frequency fo of the dielectric resonator. If the load resistance value viewed from the second gate pad is set to R, the maximum oscillation output occurs. Accordingly this oscillator enables to set the oscillation conditions between the source and gate pads of the FET, and the output matching conditions between the second gate pad and the output terminal separately, and thus allows to set the oscillation conditions and the output matching conditions, respectively, simultaneously to the optimum values.

Abstract translation: 包括两个或更多个栅极焊盘或端子的FET和包括上述FET的反射型振荡器。 在该振荡器中，通过耦合线将介质谐振器连接到FET的第一栅极焊盘，并且输出端子连接到第二焊盘。 当FET的漏极焊盘连接到地，并且将适当的电容电抗值加到源极焊盘上时，在第一栅极焊盘上出现负的电阻-R，因此，振荡发生在谐振频率fo 介质谐振器。 如果从第二栅极焊盘观察的负载电阻值设定为R，则发生最大振荡输出。 因此，该振荡器能够分别设置FET的源极和栅极焊盘之间的振荡条件以及第二栅极焊盘和输出端子之间的输出匹配条件，并且因此允许分别设置振荡条件和输出匹配条件 ，同时达到最佳值。

公开(公告)号：USRE29218E

公开(公告)日：1977-05-10

申请号：US729286

申请日：1976-10-04

Applicant: Shinzo Anazawa ,  Seiichi Ueno ,  Isamu Nagasako ,  Shigeru Sando

Inventor： Shinzo Anazawa ,  Seiichi Ueno ,  Isamu Nagasako ,  Shigeru Sando

IPC: H01L23/498 ,  H01L23/66

CPC classification number: H01L23/49811 ,  H01L23/66 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L24/48

Abstract: A packaged semiconductor device for use at ultra-high frequencies is characterized by improved high frequency characteristics as a result of reduced stay capacitance and reduced energy loss. The device includes a dielectric substrate and at least two conductor layers each of which is integral and extends over the top, side, and bottom surfaces of the dielectric substrate. No part of the conductor layer on the top surface overlaps the part on the bottom surface when viewed in a direction normal to the substrate.

公开(公告)号：US3946428A

公开(公告)日：1976-03-23

申请号：US506872

申请日：1974-09-17

Applicant: Shinzo Anazawa ,  Seiichi Ueno ,  Isamu Nagasako ,  Tadashi Nawa ,  Toshiaki Irie ,  Shigeru Sando

Inventor： Shinzo Anazawa ,  Seiichi Ueno ,  Isamu Nagasako ,  Tadashi Nawa ,  Toshiaki Irie ,  Shigeru Sando

IPC: H01L23/047 ,  H01L23/057 ,  H01L23/16 ,  H01L23/66 ,  H01L23/02 ,  H01L25/04

CPC classification number: H01L23/66 ,  H01L23/047 ,  H01L23/057 ,  H01L23/16 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/49175 ,  H01L24/48 ,  H01L24/49 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/12032 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/16195 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/30111 ,  H01L2924/3025

Abstract: A semiconductor package device characterized by improved operation at ultra-high frequencies and by improved heat dissipation, includes an auxiliary metal stud mounted on a metal substrate. A semiconductor element, such as a field-effect transistor or bipolar transistor, is mounted on the auxiliary stud and has at least one electrode thereof electrically connected to the stud.

Abstract translation: 一种半导体封装器件，其特征在于在超高频率下改进的操作和通过改进的散热，包括安装在金属基板上的辅助金属螺柱。 诸如场效应晶体管或双极晶体管的半导体元件安装在辅助柱上，并且其至少一个电极电连接至螺柱。