公开(公告)号：US08357993B2

公开(公告)日：2013-01-22

申请号：US13091264

申请日：2011-04-21

Applicant: Jian-Hsing Lee

Inventor： Jian-Hsing Lee

IPC: H01L23/52

CPC classification number: H01L23/5256 ,  H01L23/62 ,  H01L27/0288 ,  H01L29/0847 ,  H01L29/41758 ,  H01L29/7835 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: An ultra-high voltage device has a high voltage path established from a high voltage N-well through a first metal layer to a second metal layer, and a contact plug electrically connected between the high voltage N-well and the first metal layer. The contact plug has a distributed structure on a horizontal layout to improve the uniformity of the ultra-high voltage device such that the current in the high voltage path will be more uniform distributed so as to avoid the localized heat concentration caused by non-uniform current distribution that would damage the ultra-high voltage device. Multiple fuse apparatus are preferably connected to the first metal layer individually. Each the fuse apparatus includes a poly fuse to be burnt down when an over-load current flows therethrough.

Abstract translation: 超高压装置具有从高压N阱穿过第一金属层到第二金属层建立的高电压路径，以及电连接在高压N阱和第一金属层之间的接触插塞。 接触塞在水平布局上具有分布式结构，以提高超高压装置的均匀性，使得高压路径中的电流将更均匀地分布，以避免由不均匀电流引起的局部热集中 分配会损坏超高压设备。 多个保险丝装置优选地分别连接到第一金属层。 每个保险丝装置包括多个熔断器，当过载电流流过其中时，该熔断器被烧毁。

公开(公告)号：US07994577B2

公开(公告)日：2011-08-09

申请号：US12176166

申请日：2008-07-18

Applicant: Jiaw-Ren Shih ,  Jian-Hsing Lee

Inventor： Jiaw-Ren Shih ,  Jian-Hsing Lee

IPC: H01L27/06

CPC classification number: H01L27/0259 ,  H01L27/1203

Abstract: An electrostatic discharge (ESD) protection circuit includes a buried oxide layer; a semiconductor layer on the buried oxide layer; and a first and a second MOS device. The first MOS device includes a first gate over the semiconductor layer; a first well region having a portion underlying the first gate; and a first source region and a first drain region in the semiconductor layer. The second MOS device includes a second gate over the semiconductor layer; and a second well region having a portion underlying the first gate. The second well region is connected to a discharging node. The first well region is connected to the discharging node through the second well region, and is not directly connected to the discharging node. The second MOS device further includes a second source region and a second drain region in the semiconductor layer and adjoining the second well region.

Abstract translation: 静电放电（ESD）保护电路包括埋氧层; 掩埋氧化物层上的半导体层; 以及第一和第二MOS器件。 第一MOS器件包括半导体层上的第一栅极; 第一阱区，具有位于第一栅极下面的部分; 以及半导体层中的第一源极区域和第一漏极区域。 第二MOS器件包括半导体层上的第二栅极; 以及具有位于第一栅极下方的部分的第二阱区。 第二阱区连接到放电节点。 第一阱区域通过第二阱区域连接到放电节点，并且不直接连接到放电节点。 第二MOS器件还包括半导体层中的第二源极区域和第二漏极区域并与第二阱区域邻接。

公开(公告)号：US07910999B2

公开(公告)日：2011-03-22

申请号：US12342294

申请日：2008-12-23

Applicant: Jian-Hsing Lee ,  Shui-Hunyi Chen

Inventor： Jian-Hsing Lee ,  Shui-Hunyi Chen

IPC: H01L23/62

CPC classification number: H01L27/0255

Abstract: The invention describes a structure and a process for providing ESD semiconductor protection with reduced input capacitance. The structure consists of heavily doped P+ guard rings surrounding the I/O ESD protection device and the Vcc to Bss protection device. In addition, there is a heavily doped N+ guard ring surrounding the I/O protection device its P+ guard ring. The guard rings enhance structure diode elements providing enhanced ESD energy discharge path capability enabling the elimination of a specific conventional Vss to I/O pad ESD protection device. This reduces the capacitance seen by the I/O circuit while still providing adequate ESD protection for the active circuit devices.

Abstract translation: 本发明描述了一种用于提供具有降低的输入电容的ESD半导体保护的结构和工艺。 该结构由围绕I / O ESD保护器件和Vcc至Bss保护器件的重掺杂P +保护环组成。 另外，在I / O保护器件的P +保护环周围还有一个重掺杂的N +保护环。 保护环增强结构二极管元件，提供增强的ESD能量放电路径能力，从而能够消除特定的常规Vss至I / O焊盘ESD保护器件。 这降低了I / O电路所看到的电容，同时为有源电路器件提供足够的ESD保护。

公开(公告)号：US07826193B2

公开(公告)日：2010-11-02

申请号：US11585011

申请日：2006-10-23

Applicant: Dah-Jyh Perng ,  Shui-Hung Chen ,  Jian-Hsing Lee ,  Huang Yung-Sheng

Inventor： Dah-Jyh Perng ,  Shui-Hung Chen ,  Jian-Hsing Lee ,  Huang Yung-Sheng

IPC: H02H9/00

CPC classification number: H01L23/60 ,  H01L27/0288 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention relates to an electrostatic discharge (ESD) protection scheme and particularly to a string contact structure for an improved ESD performance. In an embodiment, the invention provides a method for forming an ESD protection circuit for protecting an internal circuit from damage due to an ESD voltage appearing on a pad coupled to a clamp device including a first terminal and a second terminal. The method includes forming a string contact along the first terminal and the second terminal of the clamp device. The method further includes forming one or more conductive layers on the string contact to couple the first terminal and the second terminal of the clamp device to the pad and a ground pad.

Abstract translation: 本发明涉及一种静电放电（ESD）保护方案，特别涉及一种用于提高ESD性能的串接触结构。 在一个实施例中，本发明提供一种用于形成ESD保护电路的方法，用于保护内部电路免受由耦合到包括第一端子和第二端子的钳位装置的焊盘上出现的ESD电压的损害。 该方法包括沿夹持装置的第一端子和第二端子形成串接触。 该方法还包括在串接触件上形成一个或多个导电层以将夹紧装置的第一端子和第二端子耦合到焊盘和接地焊盘。

公开(公告)号：US20100200922A1

公开(公告)日：2010-08-12

申请号：US12609803

申请日：2009-10-30

Applicant: Ming-Song Sheu ,  Jian-Hsing Lee ,  Yao-Wu Feng

Inventor： Ming-Song Sheu ,  Jian-Hsing Lee ,  Yao-Wu Feng

IPC: H01L29/78 ,  H01L29/06 ,  H01L21/336 ,  H01L21/265

CPC classification number: H01L29/66681 ,  H01L21/22 ,  H01L21/265 ,  H01L27/0259 ,  H01L29/0692 ,  H01L29/0839 ,  H01L29/0847 ,  H01L29/417 ,  H01L29/41758 ,  H01L29/66393 ,  H01L29/66659 ,  H01L29/7436 ,  H01L29/7835

Abstract: Embodiments of the invention relate to an electrostatic discharge (ESD) device and method for forming an ESD device. An embodiment is an ESD protection device comprising a p well disposed in a substrate, an n well disposed in the substrate, a high voltage n well (HVNW) disposed between the p well and the n well in the substrate, a source n+ region disposed in the p well, and a plurality of drain n+ regions disposed in the n well.

Abstract translation: 本发明的实施例涉及用于形成ESD装置的静电放电（ESD）装置和方法。 一个实施例是ESD保护装置，其包括：良好地布置在衬底中，n阱设置在衬底中;高压n阱（HVNW），其设置在衬底中的p阱和n阱之间;源极n +区域设置在 p阱以及设置在n阱中的多个漏极n +区域。

公开(公告)号：US07566935B2

公开(公告)日：2009-07-28

申请号：US11713193

申请日：2007-03-01

Applicant: Shu Huei Lin ,  Jian Hsing Lee ,  Shao Chang Huang ,  Cheng Hsu Wu ,  Chuan Ying Lee

Inventor： Shu Huei Lin ,  Jian Hsing Lee ,  Shao Chang Huang ,  Cheng Hsu Wu ,  Chuan Ying Lee

IPC: H01L23/62

CPC classification number: H01L27/0266 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An electrostatic discharge (ESD) structure connected to a bonding pad in an integrated circuit comprising: a P-type substrate with one or more first P+ regions connected to a low voltage supply (GND), a first Nwell formed in the P-type substrate, one or more second P+ regions disposed inside the first Nwell and connected to the bonding pad, at least one first N+ region disposed outside the first Nwell but in the P-type substrate and connected to the GND, at least one second N+ region disposed outside the first Nwell but in the P-type substrate and connected to the bonding pad, wherein the second N+ region is farther away from the first Nwell than the first N+ region, and at least one conductive material disposed above the P-type substrate between the first and second N+ regions and coupled to the GND, wherein the first N+ region, the second N+ region and the conductive material form the source, drain and gate of an NMOS transistor, respectively, and the first P+ region is farther away from the first Nwell than the NMOS transistor.

Abstract translation: 一种连接到集成电路中的接合焊盘的静电放电（ESD）结构，包括：具有连接到低电压源（GND）的一个或多个第一P +区的P型衬底，形成在P型衬底中的第一Nwell 设置在所述第一Nwell内并连接到所述接合焊盘的一个或多个第二P +区域，设置在所述第一N阱之外但在所述P型衬底中并连接到所述GND的至少一个第一N +区域，设置至少一个第二N +区域 在第一N阱之外，但是在P型衬底中并连接到焊盘，其中第二N +区域比第一N +区域远离第一Nwell区域，并且至少一个导电材料设置在P型衬底之上 第一N +区和第二N +区，并且耦合到GND，其中第一N +区，第二N +区和导电材料分别形成NMOS晶体管的源极，漏极和栅极，并且第一P +区域更远 从第一个Nwell比NMOS晶体管。

公开(公告)号：US07420793B2

公开(公告)日：2008-09-02

申请号：US11332565

申请日：2006-01-12

Applicant: Shao-Chang Huang ,  Jian-Hsing Lee ,  Yi-Hsun Wu ,  Jiaw-Ren Shih

Inventor： Shao-Chang Huang ,  Jian-Hsing Lee ,  Yi-Hsun Wu ,  Jiaw-Ren Shih

IPC: H02H9/00

CPC classification number: H01L27/0266 ,  H01L27/0255

Abstract: A circuit system is disclosed for protecting a capacitor coupled between a voltage supply node and a complementary voltage supply node from an ESD. The circuit system includes at least one NMOS transistor having a drain coupled to the voltage supply node, a source and a gate together coupled to the complementary voltage supply node, and at least one diode chain having one or more diodes serially coupled between the voltage supply node and the complementary voltage supply node. During an ESD event, the diode chain and the NMOS transistor dissipate an ESD current from the voltage supply node to the complementary voltage supply node, thereby protecting the capacitor from ESD induced damages.

Abstract translation: 公开了一种用于保护耦合在电压供应节点和互补电压供应节点之间的电容器与ESD的电路系统。 电路系统包括至少一个NMOS晶体管，其具有耦合到电压供应节点的漏极，一起耦合到互补电源节点的源极和至少一个二极管链，其具有串联耦合在电压源之间的一个或多个二极管 节点和互补电源节点。 在ESD事件期间，二极管链和NMOS晶体管消耗从电压供应节点到互补电源节点的ESD电流，从而保护电容器免受ESD引起的损坏。

公开(公告)号：US07385252B2

公开(公告)日：2008-06-10

申请号：US10950844

申请日：2004-09-27

Applicant: Jian-Hsing Lee ,  Deng-Shun Chang

Inventor： Jian-Hsing Lee ,  Deng-Shun Chang

IPC: H01L23/62

CPC classification number: H01L27/0277 ,  H01L27/0255

Abstract: An electrostatic discharge (ESD) protection device includes a diode located in a substrate and an N-type metal oxide semiconductor (NMOS) device located in the substrate adjacent the diode, wherein both the diode and the NMOS are coupled to an input device, and at least a portion of the diode and at least a portion of the NMOS device collectively form an ESD protection device.

Abstract translation: 静电放电（ESD）保护装置包括位于衬底中的二极管和位于与二极管相邻的衬底中的N型金属氧化物半导体（NMOS）器件，其中二极管和NMOS都耦合到输入器件，以及 二极管的至少一部分和NMOS器件的至少一部分共同形成ESD保护器件。

公开(公告)号：US20080093672A1

公开(公告)日：2008-04-24

申请号：US11585011

申请日：2006-10-23

Applicant: D. J. Perng ,  Shui-Hung Chen ,  Jian-Hsing Lee ,  Huang Yung-Sheng

Inventor： D. J. Perng ,  Shui-Hung Chen ,  Jian-Hsing Lee ,  Huang Yung-Sheng

IPC: H01L23/62

CPC classification number: H01L23/60 ,  H01L27/0288 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention relates to an electrostatic discharge (ESD) protection scheme and particularly to a string contact structure for an improved ESD performance. In an embodiment, the invention provides a method for forming an ESD protection circuit for protecting an internal circuit from damage due to an ESD voltage appearing on a pad coupled to a clamp device including a first terminal and a second terminal. The method includes forming a string contact along the first terminal and the second terminal of the clamp device. The method further includes forming one or more conductive layers on the string contact to couple the first terminal and the second terminal of the clamp device to the pad and a ground pad.

Abstract translation: 本发明涉及一种静电放电（ESD）保护方案，特别涉及一种用于提高ESD性能的串接触结构。 在一个实施例中，本发明提供一种用于形成ESD保护电路的方法，用于保护内部电路免受由耦合到包括第一端子和第二端子的钳位装置的焊盘上出现的ESD电压的损害。 该方法包括沿夹持装置的第一端子和第二端子形成串接触。 该方法还包括在串接触件上形成一个或多个导电层以将夹紧装置的第一端子和第二端子耦合到焊盘和接地焊盘。

公开(公告)号：US07247543B2

公开(公告)日：2007-07-24

申请号：US11072014

申请日：2005-03-04

Applicant: Jiaw-Ren Shih ,  Jian-Hsing Lee ,  Shui-Hung Chen

Inventor： Jiaw-Ren Shih ,  Jian-Hsing Lee ,  Shui-Hung Chen

IPC: H01L23/62

CPC classification number: H01L27/0251

Abstract: A decoupling capacitor with increased resistance to electrostatic discharge (ESD) is provided on an integrated circuit (IC). The capacitor may be single or multi-fingered. In one example, the capacitor includes first and second electrodes separated by a dielectric material, a source positioned proximate to the first electrode, and a floating drain positioned proximate to the first electrode and separated from the source by the first electrode. A parasitic element, modeled as a bipolar junction transistor (BJT), is formed by current interactions between the source, the floating drain, and a doped area. The floating drain provides a constant potential region at the base of the BJT, which minimizes ESD damage to the IC.

Abstract translation: 在集成电路（IC）上提供了具有增加的静电放电阻抗（ESD）的去耦电容器。 电容器可以是单指或多指。 在一个示例中，电容器包括由电介质材料隔开的第一和第二电极，靠近第一电极定位的源，以及靠近第一电极定位并与第一电极分离的浮动漏极。 通过源极，浮置漏极和掺杂区域之间的电流相互作用形成了被建模为双极结型晶体管（BJT）的寄生元件。 浮动漏极在BJT的基极处提供恒定的电位区域，从而最大程度降低对IC的ESD损坏。