公开(公告)号：US20080026528A1

公开(公告)日：2008-01-31

申请号：US11867137

申请日：2007-10-04

Applicant: Jack Yuan ,  Jacob Haskell

Inventor： Jack Yuan ,  Jacob Haskell

IPC: H01L21/8247

CPC classification number: H01L27/11521 ,  G11C16/0416 ,  G11C16/0458 ,  H01L27/115 ,  H01L27/11524 ,  H01L29/66825 ,  H01L29/7887

Abstract: Rows of memory cells are electrically isolated from one another by trenches formed in the substrate between the rows that are filled with a dielectric, commonly called “shallow trench isolation” or “STI.” Discontinuous source and drain regions of the cells are connected together by column oriented bit lines, preferably made of doped polysilicon, that extend in the column direction on top of the substrate. This structure is implemented in a flash memory array of cells having either one floating gate per cell or at least two floating gates per cell. A process of making a dual-floating gate memory cell array includes etching the word lines twice along their lengths, once to form openings through which source and drain implants are made and in which the conductive bit lines are formed, and second to form individual floating gates with a select transistor gate positioned between them that also serves to erase charge from the adjacent floating gates.

Abstract translation: 存储单元的行通过在填充有电介质的行之间的衬底中形成的沟槽彼此电隔离，通常称为“浅沟槽隔离”或“STI”。 电池的不连续源极和漏极区域通过列取向的位线连接在一起，优选地由掺杂多晶硅制成，其在衬底顶部的列方向上延伸。 该结构在每个单元具有一个浮动栅极或每个单元的至少两个浮动栅极的单元的闪速存储器阵列中实现。 制造双浮置栅极存储单元阵列的过程包括沿着它们的长度蚀刻字线两次，以形成开口，通过该开口形成源极和漏极注入，并且其中形成导电位线，并且其中形成单独浮置 位于它们之间的选择晶体管栅极的栅极也用于从相邻的浮动栅极擦除电荷。

公开(公告)号：US07288455B2

公开(公告)日：2007-10-30

申请号：US11227334

申请日：2005-09-14

Applicant: Jack H. Yuan ,  Jacob Haskell

Inventor： Jack H. Yuan ,  Jacob Haskell

IPC: H01L21/336

CPC classification number: H01L27/11521 ,  G11C16/0416 ,  G11C16/0458 ,  H01L27/115 ,  H01L27/11524 ,  H01L29/66825 ,  H01L29/7887

Abstract: Rows of memory cells are electrically isolated from one another by trenches formed in the substrate between the rows that are filled with a dielectric, commonly called “shallow trench isolation” or “STI.” Discontinuous source and drain regions of the cells are connected together by column oriented bit lines, preferably made of doped polysilicon, that extend in the columm direction on top of the substrate. This structure is implemented in a flash memory array of cells having either one floating gate per cell or at least two floating gates per cell. A process of making a dual-floating gate memory cell array includes etching the word lines twice along their lengths, once to form openings through which source and drain implants are made and in which the conductive bit lines are formed, and second to form individual floating gates with a select transistor gate positioned between them that also serves to erase charge from the adjacent floating gates.

Abstract translation: 存储单元的行通过在填充有电介质的行之间的衬底中形成的沟槽彼此电隔离，通常称为“浅沟槽隔离”或“STI”。 电池的不连续源极和漏极区域通过列取向的位线连接在一起，优选地由掺杂多晶硅制成，其位于衬底顶部的柱面方向。 该结构在每个单元具有一个浮动栅极或每个单元的至少两个浮动栅极的单元的闪速存储器阵列中实现。 制造双浮置栅极存储单元阵列的过程包括沿着它们的长度蚀刻字线两次，以形成开口，通过该开口形成源极和漏极注入，并且其中形成导电位线，并且其中形成单独浮置 位于它们之间的选择晶体管栅极的栅极也用于从相邻的浮动栅极擦除电荷。

公开(公告)号：US6133635A

公开(公告)日：2000-10-17

申请号：US884795

申请日：1997-06-30

Applicant: Subhas Bothra ,  Jacob Haskell

Inventor： Subhas Bothra ,  Jacob Haskell

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L23/48

CPC classification number: H01L21/76885 ,  H01L21/7682 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/5329 ,  H01L2924/0002

Abstract: Disclosed is a process for making a self-aligning conductive via structure in a semiconductor device. The process includes forming a first interconnect metallization layer over an oxide layer. Forming an etch stop layer over the first interconnect metallization layer. Forming a conductive via metallization layer over the etch stop layer. Forming a hard mask layer over the conductive via metallization layer. The process further includes producing a conductive via and an interconnect line, where the conductive via is formed from a portion of the conductive via metallization layer, and the interconnect line is formed from a portion of the first interconnect metallization layer. The conductive via is substantially aligned with the underlying interconnect line.

Abstract translation: 公开了一种在半导体器件中制造自对准导电通孔结构的方法。 该工艺包括在氧化物层上形成第一互连金属化层。 在第一互连金属化层上形成蚀刻停止层。 在蚀刻停止层上形成导电通孔金属化层。 在导电通孔金属化层上形成硬掩模层。 该方法还包括制造导电通孔和互连线，其中导电通孔由导电通孔金属化层的一部分形成，并且互连线由第一互连金属化层的一部分形成。 导电通孔基本上与下面的互连线对准。

公开(公告)号：US5776821A

公开(公告)日：1998-07-07

申请号：US916696

申请日：1997-08-22

Applicant: Jacob Haskell ,  Satyendra Sethi ,  Calvin Todd Gabriel

Inventor： Jacob Haskell ,  Satyendra Sethi ,  Calvin Todd Gabriel

IPC: H01L21/033 ,  H01L21/28 ,  H01L21/3213 ,  H01L21/3205

CPC classification number: H01L21/32136 ,  H01L21/0338 ,  H01L21/28123 ,  H01L21/32139

Abstract: A method for fabricating a semiconductor integrated circuit structure having a reduced width gate electrode. A pre-gate electrode having a width is first delineated by conventional lithography techniques. The conductive layer is partially etched to expose a first and second pre-gate side wall. With the pre-gate side walls exposed, the structure is oxidized to grow an oxide layer on the pre-gate side walls, thereby consuming a predetermined amount of the conductive material. The newly formed oxide layer is then removed to reduce the pre-gate width while retaining at least a portion of an oxide layer above the conductive layer as a mask. The reduced width gate electrode is completed by etching the remaining unmasked conductive layer.

Abstract translation: 一种制造半导体集成电路结构的方法，该半导体集成电路结构具有减小宽度的栅极 首先通过常规光刻技术描绘具有宽度的预栅极电极。 导电层被部分蚀刻以暴露第一和第二预栅极侧壁。 在栅极侧壁暴露的情况下，该结构被氧化以在栅极侧壁上生长氧化物层，从而消耗预定量的导电材料。 然后去除新形成的氧化物层以降低预栅极宽度，同时将导电层上方的氧化物层的至少一部分保留为掩模。 通过蚀刻剩余的未屏蔽导电层来完成减小宽度的栅电极。

公开(公告)号：US07541237B2

公开(公告)日：2009-06-02

申请号：US11867137

申请日：2007-10-04

Applicant: Jack H. Yuan ,  Jacob Haskell

Inventor： Jack H. Yuan ,  Jacob Haskell

IPC: H01L21/8238

CPC classification number: H01L27/11521 ,  G11C16/0416 ,  G11C16/0458 ,  H01L27/115 ,  H01L27/11524 ,  H01L29/66825 ,  H01L29/7887

Abstract: Rows of memory cells are electrically isolated from one another by trenches formed in the substrate between the rows that are filled with a dielectric, commonly called “shallow trench isolation” or “STI.” Discontinuous source and drain regions of the cells are connected together by column oriented bit lines, preferably made of doped polysilicon, that extend in the column direction on top of the substrate. This structure is implemented in a flash memory array of cells having either one floating gate per cell or at least two floating gates per cell. A process of making a dual-floating gate memory cell array includes etching the word lines twice along their lengths, once to form openings through which source and drain implants are made and in which the conductive bit lines are formed, and second to form individual floating gates with a select transistor gate positioned between them that also serves to erase charge from the adjacent floating gates.

Abstract translation: 存储单元的行通过在填充有电介质的行之间的衬底中形成的沟槽彼此电隔离，通常称为“浅沟槽隔离”或“STI”。 电池的不连续源极和漏极区域通过列取向的位线连接在一起，优选地由掺杂多晶硅制成，其在衬底顶部的列方向上延伸。 该结构在每个单元具有一个浮动栅极或每个单元的至少两个浮动栅极的单元的闪速存储器阵列中实现。 制造双浮置栅极存储单元阵列的过程包括沿着它们的长度蚀刻字线两次，以形成开口，通过该开口形成源极和漏极注入，并且其中形成导电位线，并且其中形成单独浮置 位于它们之间的选择晶体管栅极的栅极也用于从相邻的浮动栅极擦除电荷。

公开(公告)号：US06512263B1

公开(公告)日：2003-01-28

申请号：US09667344

申请日：2000-09-22

Applicant: Jack H. Yuan ,  Jacob Haskell

Inventor： Jack H. Yuan ,  Jacob Haskell

IPC: H01L29788

CPC classification number: H01L27/11521 ,  G11C16/0416 ,  G11C16/0458 ,  H01L27/115 ,  H01L27/11524 ,  H01L29/66825 ,  H01L29/7887

Abstract: Rows of memory cells are electrically isolated from one another by trenches formed in the substrate between the rows that are filled with a dielectric, commonly called “shallow trench isolation” or “STI.” Discontinuous source and drain regions of the cells are connected together by column oriented bit lines, preferably made of doped polysilicon, that extend in the column direction on top of the substrate. This structure is implemented in a flash memory array of cells having either one floating gate per cell or at least two floating gates per cell. A process of making a dual-floating gate memory cell array includes etching the word lines twice along their lengths, once to form openings through which source and drain implants are made and in which the conductive bit lines are formed, and second to form individual floating gates with a select transistor gate positioned between them that also serves to erase charge from the adjacent floating gates.

公开(公告)号：US06297170B1

公开(公告)日：2001-10-02

申请号：US09102797

申请日：1998-06-23

Applicant: Calvin Todd Gabriel ,  Jacob Haskell ,  Satyendra Sethi

Inventor： Calvin Todd Gabriel ,  Jacob Haskell ,  Satyendra Sethi

IPC: H01L21302

CPC classification number: H01L21/32139

Abstract: The present invention relates to semiconductor devices in general, and more particularly to semiconductor devices having anti-reflective coatings to aid in the patterning of a reflective layer thereon to form, for example, a gate electrode. The invention also relates to methods for making a semiconductor having a patterned reflective layer.

Abstract translation: 本发明一般涉及半导体器件，更具体地涉及具有抗反射涂层的半导体器件，以帮助其上形成例如栅电极的反射层。 本发明还涉及制造具有图案化反射层的半导体的方法。

公开(公告)号：US06953964B2

公开(公告)日：2005-10-11

申请号：US10822966

申请日：2004-04-12

Applicant: Jack H. Yuan ,  Jacob Haskell

Inventor： Jack H. Yuan ,  Jacob Haskell

IPC: H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L27/11521 ,  G11C16/0416 ,  G11C16/0458 ,  H01L27/115 ,  H01L27/11524 ,  H01L29/66825 ,  H01L29/7887

Abstract: Rows of memory cells are electrically isolated from one another by trenches formed in the substrate between the rows that are filled with a dielectric, commonly called “shallow trench isolation” or “STI.” Discontinuous source and drain regions of the cells are connected together by column oriented bit lines, preferably made of doped polysilicon, that extend in the column direction on top of the substrate. This structure is implemented in a flash memory array of cells having either one floating gate per cell or at least two floating gates per cell. A process of making a dual-floating gate memory cell array includes etching the word lines twice along their lengths, once to form openings through which source and drain implants are made and in which the conductive bit lines are formed, and second to form individual floating gates with a select transistor gate positioned between them that also serves to erase charge from the adjacent floating gates.

Abstract translation: 存储单元的行通过在填充有电介质的行之间的衬底中形成的沟槽彼此电隔离，通常称为“浅沟槽隔离”或“STI”。 电池的不连续源极和漏极区域通过列取向的位线连接在一起，优选地由掺杂多晶硅制成，其在衬底顶部的列方向上延伸。 该结构在每个单元具有一个浮动栅极或每个单元的至少两个浮动栅极的单元的闪速存储器阵列中实现。 制造双浮置栅极存储单元阵列的过程包括沿着它们的长度蚀刻字线两次，以形成开口，通过该开口形成源极和漏极注入，并且其中形成导电位线，并且其中形成单独浮置 位于它们之间的选择晶体管栅极的栅极也用于从相邻的浮动栅极擦除电荷。

公开(公告)号：US06723604B2

公开(公告)日：2004-04-20

申请号：US10265066

申请日：2002-10-03

Applicant: Jack H. Yuan ,  Jacob Haskell

Inventor： Jack H. Yuan ,  Jacob Haskell

IPC: H01L21336

CPC classification number: H01L27/11521 ,  G11C16/0416 ,  G11C16/0458 ,  H01L27/115 ,  H01L27/11524 ,  H01L29/66825 ,  H01L29/7887

Abstract: Rows of memory cells are electrically isolated from one another by trenches formed in the substrate between the rows that are filled with a dielectric, commonly called “shallow trench isolation” or “STI.” Discontinuous source and drain regions of the cells are connected together by column oriented bit lines, preferably made of doped polysilicon, that extend in the column direction on top of the substrate. This structure is implemented in a flash memory array of cells having either one floating gate per cell or at least two floating gates per cell. A process of making a dual-floating gate memory cell array includes etching the word lines twice along their lengths, once to form openings through which source and drain implants are made and in which the conductive bit lines are formed, and second to form individual floating gates with a select transistor gate positioned between them that also serves to erase charge from the adjacent floating gates.

公开(公告)号：US20060007767A1

公开(公告)日：2006-01-12

申请号：US11227334

申请日：2005-09-14

Applicant: Jack Yuan ,  Jacob Haskell

Inventor： Jack Yuan ,  Jacob Haskell

IPC: G11C7/00

CPC classification number: H01L27/11521 ,  G11C16/0416 ,  G11C16/0458 ,  H01L27/115 ,  H01L27/11524 ,  H01L29/66825 ,  H01L29/7887

Abstract: Rows of memory cells are electrically isolated from one another by trenches formed in the substrate between the rows that are filled with a dielectric, commonly called “shallow trench isolation” or “STI.” Discontinuous source and drain regions of the cells are connected together by column oriented bit lines, preferably made of doped polysilicon, that extend in the columm direction on top of the substrate. This structure is implemented in a flash memory array of cells having either one floating gate per cell or at least two floating gates per cell. A process of making a dual-floating gate memory cell array includes etching the word lines twice along their lengths, once to form openings through which source and drain implants are made and in which the conductive bit lines are formed, and second to form individual floating gates with a select transistor gate positioned between them that also serves to erase charge from the adjacent floating gates.

Abstract translation: 存储单元的行通过在填充有电介质的行之间的衬底中形成的沟槽彼此电隔离，通常称为“浅沟槽隔离”或“STI”。 电池的不连续源极和漏极区域通过列取向的位线连接在一起，优选地由掺杂多晶硅制成，其位于衬底顶部的柱面方向。 该结构在每个单元具有一个浮动栅极或每个单元的至少两个浮动栅极的单元的闪速存储器阵列中实现。 制造双浮置栅极存储单元阵列的过程包括沿着它们的长度蚀刻字线两次，以形成开口，通过该开口形成源极和漏极注入，并且其中形成导电位线，并且其中形成单独浮置 位于它们之间的选择晶体管栅极的栅极也用于从相邻的浮动栅极擦除电荷。