公开(公告)号：US4330930A

公开(公告)日：1982-05-25

申请号：US120741

申请日：1980-02-12

申请人： Richard M. Morley ,  Jagir S. Multani ,  J. S. Sandhu

发明人： Richard M. Morley ,  Jagir S. Multani ,  J. S. Sandhu

IPC分类号： H01L21/8247 ,  H01L29/788 ,  H01L29/792 ,  H01L21/18

CPC分类号： H01L29/792

摘要： An electrically alterable read only memory (EAROM) having a tunneling layer of an insulating material such as silicon dioxide which is grown on the substrate by thermal oxidation carried out at low pressure and a layer of silicon nitride laid down on the tunneling layer by a low-pressure chemical vapor deposition, the interface of the two layers forming a charge storage area with the EAROM having improved read/write switching capability and quality, and improved reliability and memory retentivity characteristics.

摘要翻译： 具有通过在低压下进行的热氧化而在衬底上生长的绝缘材料（例如二氧化硅）的隧穿层的电可更换的只读存储器（EAROM）和铺设在隧道层上的氮化硅层低 压力化学气相沉积，两层的界面形成电荷存储区域，EAROM具有改进的读/写切换能力和质量，以及改进的可靠性和记忆保持特性。

公开(公告)号：US4775550A

公开(公告)日：1988-10-04

申请号：US870234

申请日：1986-06-03

申请人： John K. Chu ,  Sanjiv K. Mittal ,  John T. Orton ,  Jagir S. Multani ,  Robert Jecmen

发明人： John K. Chu ,  Sanjiv K. Mittal ,  John T. Orton ,  Jagir S. Multani ,  Robert Jecmen

IPC分类号： H01L21/3205 ,  H01L21/768 ,  B05D3/06 ,  B05D5/12

CPC分类号： H01L21/76819

摘要： A planarization process for a double metal very large scale integration (VLSI) technology is disclosed. To compensate for an irregular surface topology encountered in a dielectric medium between the two metals, a CVD dielectric layer and a glass layer are first deposited above the first metal. Then an etch-back process is used to uniformly etch back the CVD dielectric and the glass layers at the same rate, leaving a planarized surface for subsequent deposition of a second dielectric layer and a second metal layer.

摘要翻译： 公开了一种用于双金属超大规模集成（VLSI）技术的平面化工艺。 为了补偿在两种金属之间的介电介质中遇到的不规则表面拓扑，首先在第一金属之上沉积CVD电介质层和玻璃层。 然后使用回蚀刻工艺以相同的速率均匀地回蚀CVD电介质和玻璃层，留下平坦的表面，用于随后沉积第二介电层和第二金属层。

公开(公告)号：US4456978A

公开(公告)日：1984-06-26

申请号：US381704

申请日：1982-05-25

申请人： Richard M. Morley ,  Jagir S. Multani ,  J. S. Sandhu

发明人： Richard M. Morley ,  Jagir S. Multani ,  J. S. Sandhu

IPC分类号： H01L29/792 ,  G11C11/40

CPC分类号： H01L29/792

摘要： An electrically alterable read only memory (EAROM) having a tunneling layer of an insulating material such as silicon dioxide which is grown on the substrate by thermal oxidation carried out at low pressure and a layer of silicon nitride laid down on the tunneling layer by a low-pressure chemical vapor deposition, the interface of the two layers forming a charge storage area with the EAROM having improved read/write switching capability and quality, and improved reliability and memory retentivity characteristics.

摘要翻译： 具有通过在低压下进行的热氧化而在衬底上生长的绝缘材料（例如二氧化硅）的隧穿层的电可更换的只读存储器（EAROM）和铺设在隧道层上的氮化硅层低 压力化学气相沉积，两层的界面形成电荷存储区域，EAROM具有改进的读/写切换能力和质量，以及改进的可靠性和记忆保持特性。

公开(公告)号：US4243937A

公开(公告)日：1981-01-06

申请号：US27842

申请日：1979-04-06

申请人： Jagir S. Multani ,  Jagtar S. Sandhu

发明人： Jagir S. Multani ,  Jagtar S. Sandhu

IPC分类号： G11C16/04 ,  G11C17/00 ,  G11C29/00 ,  G11C29/24 ,  G11C29/50 ,  H01L21/8247 ,  H01L29/788 ,  H01L29/792 ,  G01R31/22

CPC分类号： G11C29/50016 ,  G11C29/50 ,  G06F2201/81 ,  G11C16/04

摘要： A method for testing a microelectronic circuit to detect process defects which affect first and second characteristics of the circuit elements thereof. The circuit is formed on a semiconductor chip in proximity with an independent test element. The test element is not connected to and does not form a part of the circuit. The circuit elements are tested to detect process defects which affect the first characteristic thereof. The test element is tested to detect process defects which affect the second characteristics of both the circuit elements and the test element. The results of the test on the test element are relied on to determine the acceptability of the second characteristics of the circuit elements. The test on the test element for said second characteristic may be performed at the same time the circuit elements are being tested for said first characteristic.

摘要翻译： 一种用于测试微电子电路以检测影响其电路元件的第一和第二特性的工艺缺陷的方法。 电路形成在靠近独立测试元件的半导体芯片上。 测试元件不连接到电路，不构成电路的一部分。 测试电路元件以检测影响其第一特性的工艺缺陷。 测试测试元件以检测影响电路元件和测试元件的第二特性的工艺缺陷。 依靠测试元件的测试结果来确定电路元件的第二特性的可接受性。 用于所述第二特性的测试元件的测试可以在电路元件被测试所述第一特性的同时进行。

公开(公告)号：US4521796A

公开(公告)日：1985-06-04

申请号：US550725

申请日：1983-11-14

申请人： Kamal Rajkanan ,  Jagir S. Multani

发明人： Kamal Rajkanan ,  Jagir S. Multani

IPC分类号： H01L29/78 ,  H01L29/792

CPC分类号： H01L29/78 ,  H01L29/792

摘要： An Electrically Alterable Read Only Memory device including at least one cell in a substrate having source and drain channels with a memory gate region therebetween with the substrate in the memory gate region having therein a first impurity material of a first conductivity type to establish a desired write threshold voltage and a second impurity material of a second conductivity type opposite to said first type to tailor the surface concentration profiles of the impurity material in the memory gate region of the substrate.

摘要翻译： 一种电可更改的只读存储器件，其包括具有源极和漏极通道的衬底中的至少一个单元，存储器栅极区域在其间，存储器栅极区域中的衬底具有第一导电类型的第一杂质材料，以建立期望的写入 阈值电压和与所述第一类型相反的第二导电类型的第二杂质材料，以调整所述衬底的存储器栅极区域中的杂质材料的表面浓度分布。