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1.发明授权公开(公告)号：US06754616B1
公开(公告)日：2004-06-22
申请号：US09494821
申请日：2000-01-31
IPC分类号： G06G762
CPC分类号： G06F17/5036 , H01F19/08
摘要： A method of simulating the electrical behavior of an ideal transformer. The representation of the ideal transformer is frequency independent and can be used to simulate the behavior of an ideal transformer over the frequency range from DC to infinity. In one embodiment, the ideal transformer is represented as having an input sub-circuit and an output sub-circuit. Each sub-circuit includes a resistor connected in parallel across a current controlled current source. The input current, output current, current sources, and resistances are scaled by a scaling factor representing the turns ratio between the primary and secondary windings of a physical transformer. In the present invention, the current sources are responsible for the current scaling and the resistors are responsible for the impedance scaling. The circuit elements of the representation may be used as the basis for generating a set of input parameters for a circuit emulation program.
摘要翻译： 一种模拟理想变压器电气特性的方法。 理想变压器的表示是频率无关的，可用于模拟从直流到无限的频率范围内的理想变压器的性能。 在一个实施例中，理想变压器被表示为具有输入子电路和输出子电路。 每个子电路包括在电流控制的电流源上并联连接的电阻器。 输入电流，输出电流，电流源和电阻通过表示物理变压器的初级和次级绕组之间的匝数比的比例因子来缩放。 在本发明中，电流源负责电流缩放，电阻负责阻抗缩放。 该表示的电路元件可以用作生成用于电路仿真程序的一组输入参数的基础。
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公开(公告)号：US5817533A
公开(公告)日：1998-10-06
申请号：US692800
申请日：1996-07-29
摘要： Described are methods of manufacturing large substrate capacitors for multi-chip module applications and the like using procedures compatible with common semiconductor fabrication procedures. A capacitor is formed where the top electrode thereof is divided into a plurality of segmented pads which are initially electrically isolated from one another. Each segmented pad forms a capacitor with the underlying dielectric layer and bottom capacitor electrode. Each segmented capacitor is electrically tested, and defective ones are identified. A conductive layer is thereafter formed over the segmented pads such that the conductive layer is electrically isolated from the pads of defective capacitors. The conductive layer electrically couples the good capacitors in parallel to form a high-value bypass capacitor which has low parasitic inductance. Large embedded MCM bypass capacitors can thereby be fabricated with minimal impact to the overall manufacturing yield. Novel testing methods within a scanning electron microscope environment are also disclosed.
摘要翻译： 描述了使用与普通半导体制造程序兼容的程序来制造用于多芯片模块应用的大型衬底电容器等的方法。 形成电容器，其中其顶部电极被分成彼此最初电绝缘的多个分段焊盘。 每个分段焊盘与底层电介质层和底部电容器电极形成电容器。 每个分段电容器进行电气测试，并且识别有缺陷的电容器。 之后在分段焊盘上形成导电层，使得导电层与有缺陷的电容器的焊盘电绝缘。 导电层将良好的电容器并联电耦合以形成具有低寄生电感的高值旁路电容器。 因此，可以制造大型嵌入式MCM旁路电容器，对整个制造产量的影响最小。 还公开了扫描电子显微镜环境中的新型测试方法。
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公开(公告)号：US5701071A
公开(公告)日：1997-12-23
申请号：US517572
申请日：1995-08-21
CPC分类号： G05F3/262
摘要： Systems for controlling the current consumption of an integrated circuit chip and the like so as to reduce the inductive voltage drops occurring over the power supply lines within the chip and power supply lines to the chip are disclosed. The systems according to the present invention are applicable to circuits having two or more sub-circuits formed on a semiconductor substrate, each sub-circuit having two or more power supply inputs. An exemplary system comprises two or more current shunting elements formed on the substrate, with each current shunting element coupled in parallel with the power supply inputs of a selected sub-circuit. The system has at least two main power supply lines formed on the semiconductor substrate, with each selected sub-circuit having each of its power supply inputs coupled to a main power supply line. A current shunting element may comprise a Zener diode, an active shunt circuit, or equivalents thereof.
摘要翻译： 公开了用于控制集成电路芯片等的电流消耗的系统，以便减少在芯片内的电源线和芯片的电源线之间发生的感应电压降。 根据本发明的系统可应用于具有形成在半导体衬底上的两个或多个子电路的电路，每个子电路具有两个或多个电源输入。 示例性系统包括形成在衬底上的两个或更多个电流分流元件，其中每个电流分流元件与所选子电路的电源输入并联耦合。 该系统具有形成在半导体衬底上的至少两个主电源线，每个所选择的子电路的每个电源输入端连接到主电源线。 电流分流元件可以包括齐纳二极管，有源分流电路或其等同物。
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4.发明授权
公开(公告)号：US5765279A
公开(公告)日：1998-06-16
申请号：US445672
申请日：1995-05-22
IPC分类号： H01L23/12 , H01L21/48 , H01L21/822 , H01L23/50 , H01L23/538 , H01L27/01 , H01L27/04 , H05K3/34
CPC分类号： H01L21/4857 , H01L23/50 , H01L2224/16 , H01L2924/3011 , Y10T29/49144
摘要： A power distribution structure for a multichip module and a method for fabricating the same are shown. According to the method of the present invention, a base plate is provided, a plurality of mesas arranged in a pattern are formed on the base plate, the mesas having electrically conductive upper surfaces which lie substantially in a single plane. A thin, conformal dielectric layer is then formed over the exposed surfaces of the mesas and the support base and a conductive material is deposited over the dielectric material filling the area between and surrounding the mesas. The resulting structure is then planarized, as by polishing, such that the upper surfaces of the mesas and the upper surface of the conductive material surrounding the mesas lie in substantially one plane and are electrically isolated from each other by the dielectric material. A multilayered thin film structure for a multichip module may then be formed over the power distribution structure and power and ground potentials supplied to microelectronic components, such as integrated circuit chips, mounted on the surface of the thin film structure using vias routed through the thin film structure.
摘要翻译： 示出了用于多芯片模块的配电结构及其制造方法。 根据本发明的方法，提供一种基板，在基板上形成多个以图案布置的台面，台面具有基本上在单个平面内的导电上表面。 然后在台面和支撑基底的暴露的表面上形成薄的共形绝缘层，并且将导电材料沉积在填充台面之间并围绕台面的区域的电介质材料上。 然后将所得结构平坦化，如通过抛光，使得台面的上表面和围绕台面的导电材料的上表面位于基本上一个平面中并且通过电介质材料彼此电隔离。 然后可以在功率分配结构上形成用于多芯片模块的多层薄膜结构，并且使用安装在薄膜结构的表面上的微电子部件（例如集成电路芯片）提供的功率和接地电位使用通过薄膜 结构体。
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公开(公告)号：US07372627B1
公开(公告)日：2008-05-13
申请号：US11644026
申请日：2006-12-22
申请人： Richard L. Wheeler
发明人： Richard L. Wheeler
IPC分类号： G02B23/00
CPC分类号： G02B23/18
摘要： A holder for field glasses has a pair of substantially similar resilient receptacles that each has a main body with an open bottom and a narrower neck with an open top. A slot is located in each neck portion while a slit extends between each slot and its respective open bottom. The two receptacles are attached to each other so as to be parallel to one another and so that each slit generally faces the other receptacle. A pair of binoculars is inserted, ocular lens side first, through the bottoms of each main body by gapping each receptacle with the bridge of the binoculars passing through the gapped slits. Once the bridge is received within the slots of the two receptacles, the slits are degapped. Alternately, the binoculars themselves may have the form of a pair of drink receptacles.
摘要翻译： 用于野外眼镜的支架具有一对基本相似的弹性插座，每个弹性插座具有开放底部的主体和具有开口顶部的较窄的颈部。 狭槽位于每个颈部中，而狭缝在每个狭槽和其相应的开口底部之间延伸。 两个容器彼此附接以便彼此平行，并且使得每个狭缝通常面向另一容器。 一双双筒望远镜首先通过每个主体的底部插入眼镜面，每个主体通过双眼望远镜穿过有间隙的狭缝的桥梁间隔每个容器。 一旦桥被接收在两个插座的槽中，则缝隙被去除。 或者，双筒望远镜本身可以具有一对饮料容器的形式。
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6.发明授权Apparatus for equalizing signal parameters in flip chip redistribution layers 失效用于在倒装芯片再分配层中均衡信号参数的装置
公开(公告)号：US6025647A
公开(公告)日：2000-02-15
申请号：US976564
申请日：1997-11-24
IPC分类号： H01L21/60 , H01L23/498 , H01L23/48
CPC分类号： H01L24/81 , H01L23/49838 , H01L2224/81801 , H01L2924/01005 , H01L2924/01023 , H01L2924/01033 , H01L2924/014 , H01L2924/14 , H01L2924/15173 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105
摘要： Disclosed is a redistribution layer having a patterned metallization layer for use in a flip chip integrated circuit device and a method for making the same. The redistribution layer includes a plurality of slot pads arranged along a periphery of the redistribution layer. The plurality of slot pads are formed from the patterned metallization layer. An array of bump pads are arranged in an inner portion of the redistribution layer such that the plurality of slot pads surround the array of bump pads, and the array of bump pads are formed from the patterned metallization layer. The redistribution layer further includes a plurality of traces that are formed from the patterned metallization layer and are configured to interconnect the plurality of slot pads to the array of bump pads. Each of the traces has a width that is selected to substantially equalize a resistance parameter associated with each of the plurality of traces. Additionally, each trace may include a bump pad area and possibly capacitance extending stubs that may be custom sized to substantially equalize a capacitance parameter associated with each of the plurality of traces.
摘要翻译： 公开了一种具有用于倒装芯片集成电路器件的图案化金属化层的再分布层及其制造方法。 再分配层包括沿再分布层的周边布置的多个狭槽垫。 多个槽衬垫由图案化的金属化层形成。 凸点焊盘的阵列布置在再分配层的内部，使得多个槽焊盘围绕凸块焊盘的阵列，并且凸块焊盘的阵列由图案化的金属化层形成。 再分布层还包括由图案化的金属化层形成的多条迹线，并被配置为将多个槽焊盘互连到凸块焊盘的阵列。 每个迹线具有被选择为基本上均衡与多个迹线中的每一个相关联的电阻参数的宽度。 另外，每个迹线可以包括凸块焊盘区域和可能的电容扩展短截线，其可以被定制成大小以基本上均衡与多个迹线中的每一个相关联的电容参数。
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公开(公告)号：US06483341B2
公开(公告)日：2002-11-19
申请号：US09754564
申请日：2001-01-04
IPC分类号： H03K1716
摘要： An apparatus for regulating resonance in a micro-chip has been developed. The method includes connecting a de-coupled capacitance across the supply and ground voltages, and connecting a band-pass shunt regulator that is in parallel to the capacitor across the supply and ground voltages. The regulator will short circuit the supply and ground voltages at a pre-determined frequency to reduce the resonance effect on the micro-chip.
摘要翻译： 已经开发了用于调节微芯片中的共振的装置。 该方法包括在电源和接地电压之间连接去耦合电容，以及在电源和接地电压之间连接与电容器并联的带通分流调节器。 调节器将以预定频率将电源和接地电压短路，以减少对微芯片的共振效应。
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公开(公告)号：US06034332A
公开(公告)日：2000-03-07
申请号：US038805
申请日：1998-03-11
IPC分类号： H01L23/12 , H01L21/48 , H01L21/822 , H01L23/50 , H01L23/538 , H01L27/01 , H01L27/04 , H05K1/03
CPC分类号： H01L21/4857 , H01L23/50 , H01L2224/16 , H01L2924/3011 , Y10T29/49144
摘要： A power distribution structure for a multichip module including, a base plate, a plurality of mesas arranged in a pattern are formed on the base plate, the mesas having electrically conductive upper surfaces which lie substantially in a single plane. A thin, conformal dielectric layer is formed over the exposed side surfaces of the mesas and the exposed surfaces of the support base and a conductive material is deposited over the dielectric material filling the area between and surrounding the mesas. The upper surfaces of the mesas and the upper surface of the conductive material surrounding the mesas lie in substantially one plane and are electrically isolated from each other by the dielectric material. A multilayered thin film structure for a multichip module may be formed over the power distribution structure and power and ground potentials supplied to microelectronic components, such as integrated circuit chips, mounted on the surface of the thin film structure using vias routed through the thin film structure.
摘要翻译： 包括基板，以图案排列的多个台面的多芯片模块的配电结构形成在基板上，台面具有基本上位于单个平面中的导电上表面。 在台面的暴露的侧表面和支撑基底的暴露的表面之上形成薄的共形绝缘层，并且导电材料沉积在填充台面之间并围绕台面的区域的电介质材料上。 台面的上表面和围绕台面的导电材料的上表面位于基本上一个平面中并且通过介电材料彼此电隔离。 用于多芯片模块的多层薄膜结构可以在功率分配结构上形成，并且提供给微电子部件（例如集成电路芯片）的功率和接地电位，其使用通过薄膜结构布线的通孔安装在薄膜结构的表面上 。
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9.发明授权Special interconnect layer employing offset trace layout for advanced multi-chip module packages 失效采用偏移轨迹布局的高级多芯片模块封装的特殊互连层
公开(公告)号：US5508938A
公开(公告)日：1996-04-16
申请号：US125035
申请日：1993-09-21
申请人： Richard L. Wheeler
发明人： Richard L. Wheeler
CPC分类号： H01L23/5386 , H01L23/5383 , H01L2924/0002 , H01L2924/3011
摘要： A multi-layer printed wiring board design method employs establishing of critical and non-critical signal layers with first and second design rule sets assigned respectively. A configuration employing y x y' layers wherein conductors in the y and y' layers are orthogonal to x layers and y' layers are offset by approximately one-half pitch from y layers for cross talk reduction.
摘要翻译： 多层印刷线路板设计方法采用分别指定的第一和第二设计规则集建立关键和非关键信号层。 使用y x y'层的结构，其中y和y'层中的导体与x层正交并且y'层从y层偏移大约一半的间距以进行串扰降低。
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10.发明授权公开(公告)号：US06871290B2
公开(公告)日：2005-03-22
申请号：US09930373
申请日：2001-08-14
IPC分类号： H03K17/16 , H03K17/693 , G06F1/26 , G06F1/32
CPC分类号： H03K17/164 , H03K17/693
摘要： A method for reducing a magnitude of a rate of current change of an integrated circuit is provided. The method uses a plurality of transistors controlled by a finite state machine, such as a counter, to gradually reduce current sourced from a power supply. Further, the finite state machine is controlled by a micro-architectural stage that determines when the integrated circuit needs to be powered down.
摘要翻译： 提供了一种用于减小集成电路的电流变化率的幅度的方法。 该方法使用由诸如计数器的有限状态机控制的多个晶体管来逐渐减少源自电源的电流。 此外，有限状态机由微架构级控制，确定集成电路何时需要掉电。
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