公开(公告)号：US07696578B2

公开(公告)日：2010-04-13

申请号：US11349804

申请日：2006-02-08

申请人： Chia-Lin Chen ,  Min-jan Chen ,  Jau-Jey Wang

发明人： Chia-Lin Chen ,  Min-jan Chen ,  Jau-Jey Wang

IPC分类号： H01L27/092

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/7848

摘要： A PMOS device less affected by negative bias time instability (NBTI) and a method for forming the same are provided. The PMOS device includes a barrier layer over at least a portion of a gate structure, a gate spacer, and source/drain regions of a PMOS device. A stressed layer is then formed over the barrier layer. The barrier layer is preferably an oxide layer and is preferably not formed for NMOS devices.

摘要翻译： 提供了较少受负偏压时间不稳定性（NBTI）影响的PMOS器件及其形成方法。 PMOS器件在PMOS器件的栅极结构，栅极间隔物和源极/漏极区域的至少一部分上包括阻挡层。 然后在阻挡层上形成应力层。 阻挡层优选为氧化物层，优选不为NMOS器件形成。

公开(公告)号：US20070181951A1

公开(公告)日：2007-08-09

申请号：US11349804

申请日：2006-02-08

申请人： Chia-Lin Chen ,  Min-Jan Chen ,  Jau-Jey Wang

发明人： Chia-Lin Chen ,  Min-Jan Chen ,  Jau-Jey Wang

IPC分类号： H01L29/76 ,  H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/7848

摘要： A PMOS device less affected by negative bias time instability (NBTI) and a method for forming the same are provided. The PMOS device includes a barrier layer over at least a portion of a gate structure, a gate spacer, and source/drain regions of a PMOS device. A stressed layer is then formed over the barrier layer. The barrier layer is preferably an oxide layer and is preferably not formed for NMOS devices.

摘要翻译： 提供了较少受负偏压时间不稳定性（NBTI）影响的PMOS器件及其形成方法。 PMOS器件在PMOS器件的栅极结构，栅极间隔物和源极/漏极区域的至少一部分上包括阻挡层。 然后在阻挡层上形成应力层。 阻挡层优选为氧化物层，优选不为NMOS器件形成。

公开(公告)号：US06171913B2

公开(公告)日：2001-01-09

申请号：US09149256

申请日：1998-09-08

申请人： Jau-Jey Wang ,  Chaochieh Tsai ,  Jing-Meng Liu

发明人： Jau-Jey Wang ,  Chaochieh Tsai ,  Jing-Meng Liu

IPC分类号： H01L21336

CPC分类号： H01L29/66492 ,  H01L21/26586 ,  H01L29/665 ,  H01L29/66659 ,  H01L29/7835

摘要： A process is described for forming a buried, or pocket, ion implant in a semiconductor device. In particular, said pocket is limited to only the drain side of a field effect transistor. To achieve this the photoresist that is used to protect the source and drain regions during ion implantation is located at different distances from the gate pedestal. The photoresist on the source side is placed closer to the gate pedestal than it is on the drain side. As a result, when ions arrive at the surface at a sufficiently shallow angle to be able to penetrate the semiconductor regions immediately beneath the gate oxide, photoresist at the source side blocks the beam while the photoresist on the drain side is far enough away from the gate not to intercept the beam. Thus, a single asymmetrically located pocket is formed in a single step.

摘要翻译： 描述了用于在半导体器件中形成掩埋或口袋离子注入的工艺。 特别地，所述口袋仅限于场效应晶体管的漏极侧。 为了实现这一点，在离子注入期间用于保护源极和漏极区域的光致抗蚀剂位于与栅极基座不同的距离处。 源极侧的光致抗蚀剂比排水侧更靠近栅基座。 结果，当离子以足够浅的角度到达表面以能够穿过栅极氧化物正下方的半导体区域时，源极侧的光致抗蚀剂阻挡光束，而漏极侧的光致抗蚀剂远离 门不拦截梁。 因此，在单个步骤中形成单个不对称定位的袋。

公开(公告)号：US5547881A

公开(公告)日：1996-08-20

申请号：US612620

申请日：1996-03-06

申请人： Jau-Jey Wang ,  Pi-Chen Shieh ,  Pin-Nan Tseng

发明人： Jau-Jey Wang ,  Pi-Chen Shieh ,  Pin-Nan Tseng

IPC分类号： H01L27/02 ,  H01L21/266

CPC分类号： H01L27/0288

摘要： A method is described for forming a high contact resistance region within the drain region or source region of an insulated gate field effect transistor as part of a high resistance resistor for electrostatic discharge protection of the field effect transistor. The high resistance contact region is formed as part of a self aligned silicide, or salicide, contact process. Nitrogen ion implantation at the high resistance contact region into the metal which will be used to form the metal silicide low resistance contacts converts the metal at the high resistance contact region to metal nitride. Since all the metal at the high resistance contact region is converted to metal nitride there is no free metal to form metal silicide at the high resistance contact region when the low resistance metal silicide contacts are formed. Low resistance contacts to the gate electrode, source, and drain are formed using metal silicide.

摘要翻译： 描述了用于在绝缘栅场效应晶体管的漏极区域或源极区域内形成高接触电阻区域的方法，作为用于场效应晶体管的静电放电保护的高电阻电阻器的一部分。 高电阻接触区形成为自对准硅化物或自对准硅化物接触工艺的一部分。 在用于形成金属硅化物低电阻触点的金属中的高电阻接触区域的氮离子注入将高电阻接触区域处的金属转化为金属氮化物。 由于高电阻接触区域的全部金属转化为金属氮化物，所以当形成低电阻金属硅化物接触时，在高电阻接触区域不存在形成金属硅化物的游离金属。 使用金属硅化物形成与栅电极，源极和漏极的低电阻接触。

公开(公告)号：US5801090A

公开(公告)日：1998-09-01

申请号：US845608

申请日：1997-04-25

申请人： Lin-June Wu ,  Jau-Jey Wang

发明人： Lin-June Wu ,  Jau-Jey Wang

IPC分类号： H01L21/3105 ,  H01L23/544 ,  H01L21/28

CPC分类号： H01L23/544 ,  H01L21/31053 ,  H01L2223/54453 ,  H01L2924/0002 ,  Y10S438/975

摘要： The present invention is a method of protecting an alignment mark in semiconductor manufacturing process with CMP. This invention utilizes a via mask or masking blade to remove the intermetal dielectric layer on a wide clear -out window using two etching steps. One etching step is performed before intermetal dielectric layer polish. The other etching step is performed after intermetal dielectric layer polish. Thus, there is no intermetal dielectric layer remained on the alignment mark and the alignment mark keeps the original shape.

摘要翻译： 本发明是利用CMP在半导体制造工艺中保护对准标记的方法。 本发明利用通孔掩模或掩模刀片，使用两个蚀刻步骤在宽的透明窗口上去除金属间电介质层。 在金属间电介质层抛光之前进行一个蚀刻步骤。 在金属间电介质层抛光之后进行另一蚀刻步骤。 因此，在对准标记上不存在金属间电介质层，并且对准标记保持原来的形状。

公开(公告)号：US5705441A

公开(公告)日：1998-01-06

申请号：US618177

申请日：1996-03-19

申请人： Jau-Jey Wang ,  Yuan-Lung Liu

发明人： Jau-Jey Wang ,  Yuan-Lung Liu

IPC分类号： H01L21/285 ,  H01L27/02 ,  H01L21/28

CPC分类号： H01L27/0251 ,  H01L21/28518

摘要： A method is described for forming a high contact resistance region within the drain region or source region of an insulated gate field effect transistor as part of a high resistance resistor for electrostatic discharge protection of the field effect transistor. The silicide free contact region is formed as part of a self aligned silicide, or salicide, contact process. Nitrogen ion implantation followed by annealing is used to form a silicon nitride mask at the silicide free contact region. The mask prevents the formation of low contact resistance metal silicide at the silicide free contact region during the salicide process. Low resistance contacts to the gate electrode, source, and drain are formed using metal silicide.

摘要翻译： 描述了用于在绝缘栅场效应晶体管的漏极区域或源极区域内形成高接触电阻区域的方法，作为用于场效应晶体管的静电放电保护的高电阻电阻器的一部分。 无硅化物接触区域形成为自对准硅化物或自对准硅化物接触工艺的一部分。 使用氮离子注入，然后进行退火，以在无硅化物接触区域形成氮化硅掩模。 掩模防止了在自杀化处理过程中在无硅化物接触区域形成低接触电阻金属硅化物。 使用金属硅化物形成与栅电极，源极和漏极的低电阻接触。

公开(公告)号：US5508212A

公开(公告)日：1996-04-16

申请号：US429729

申请日：1996-04-27

申请人： Jau-Jey Wang ,  Ming-Hsung Chang

发明人： Jau-Jey Wang ,  Ming-Hsung Chang

IPC分类号： H01L21/265 ,  H01L21/285 ,  H01L21/336 ,  H01L21/28

CPC分类号： H01L29/6659 ,  H01L21/28518 ,  H01L29/665 ,  H01L21/26586

摘要： A salicide process for manufacturing a lightly doped drain (LDD) MOS transistor having unshorted titanium silicide gate electrode and source/drain contacts. The salicide method comprises forming a titanium (Ti) layer on the surface of the substrate, the sidewall spacers and the gate electrode. Nitrogen is implanted at a large angle into the Ti layer, especially over the sidewall spacers, thus converting all the titanium layer over the spacers to titanium nitride. Next, the titanium layer is thermally annealed forming titanium silicide on the top surface of the gate electrode and in the highly doped source/drain regions. The titanium nitride layer and any of the remaining titanium layer is etched away thereby leaving unshorted titanium silicide on the top surface of the gate electrode and in the highly doped source/drain regions. The TiN layer over the sidewall spacers prevents a titanium silicide bridge from forming between/he gate electrode and the source/drain regions during the thermal anneal process. This prevent electrical shorting between titanium silicide on the top surface of the gate electrode and the highly doped source/drain regions.

摘要翻译： 一种用于制造具有未排序的硅化钛栅电极和源极/漏极触点的轻掺杂漏极（LDD）MOS晶体管的自对准硅化物工艺。 所述自对准硅化物方法包括在所述基材的表面，所述侧壁间隔物和所述栅电极上形成钛（Ti）层。 将氮以大角度注入到Ti层中，特别是在侧壁间隔物上方，从而将间隔物上的所有钛层转化为氮化钛。 接下来，钛层在栅电极的顶表面和高掺杂源/漏区中热退火形成硅化钛。 蚀刻氮化钛层和任何剩余的钛层，从而在栅极电极的顶表面和高度掺杂的源极/漏极区域中留下未排序的硅化钛。 侧壁间隔物上的TiN层防止在热退火过程期间在硅栅极电极和源极/漏极区域之间形成钛硅化物桥。 这防止栅电极的顶表面上的硅化钛与高度掺杂的源/漏区之间的电短路。