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    Ion implant silicon nitride mask for a silicide free contact region in a self aligned silicide process
    1.
    发明授权
    Ion implant silicon nitride mask for a silicide free contact region in a self aligned silicide process 失效
    离子注入氮化硅掩模，用于自对准硅化物工艺中的无硅化物接触区域

    公开(公告)号：US5705441A

    公开(公告)日：1998-01-06

    申请号：US618177

    申请日：1996-03-19

    申请人： Jau-Jey Wang ,  Yuan-Lung Liu

    发明人： Jau-Jey Wang ,  Yuan-Lung Liu

    IPC分类号： H01L21/285 ,  H01L27/02 ,  H01L21/28

    CPC分类号： H01L27/0251 ,  H01L21/28518

    摘要： A method is described for forming a high contact resistance region within the drain region or source region of an insulated gate field effect transistor as part of a high resistance resistor for electrostatic discharge protection of the field effect transistor. The silicide free contact region is formed as part of a self aligned silicide, or salicide, contact process. Nitrogen ion implantation followed by annealing is used to form a silicon nitride mask at the silicide free contact region. The mask prevents the formation of low contact resistance metal silicide at the silicide free contact region during the salicide process. Low resistance contacts to the gate electrode, source, and drain are formed using metal silicide.

    摘要翻译： 描述了用于在绝缘栅场效应晶体管的漏极区域或源极区域内形成高接触电阻区域的方法，作为用于场效应晶体管的静电放电保护的高电阻电阻器的一部分。 无硅化物接触区域形成为自对准硅化物或自对准硅化物接触工艺的一部分。 使用氮离子注入，然后进行退火，以在无硅化物接触区域形成氮化硅掩模。 掩模防止了在自杀化处理过程中在无硅化物接触区域形成低接触电阻金属硅化物。 使用金属硅化物形成与栅电极，源极和漏极的低电阻接触。

    Bonding pad structure to minimize IMD cracking
    3.
    发明授权
    Bonding pad structure to minimize IMD cracking 有权
    粘合垫结构以最小化IMD开裂

    公开(公告)号：US07759797B2

    公开(公告)日：2010-07-20

    申请号：US11546078

    申请日：2006-10-11

    申请人： Chung Liu ,  Yuan-Lung Liu ,  Ruey-Yun Shiue

    发明人： Chung Liu ,  Yuan-Lung Liu ,  Ruey-Yun Shiue

    IPC分类号： H01L23/528

    CPC分类号： H01L24/05 ,  H01L2224/05093 ,  H01L2224/05094 ,  H01L2224/05095 ,  H01L2224/05096 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/05042 ,  H01L2924/14

    摘要： A method is disclosed of forming a bonding pad that is immune to IMD cracking. A partially processes semiconductor wafer is provided having all metal levels completed. A blanket dielectric layer is formed over the uppermost metal level. Patterning and etching said dielectric layer horizontal and vertical arrays of trenches are formed passing through the dielectric layer and separating the dielectric layer into cells. The trenches are filled with a conducting material and, after performing CMP, bonding metal patterns are deposited. Wires are bonded onto said bonding metal patters, after which a passivation layer is formed.

    摘要翻译： 公开了形成对IMD开裂免疫的接合垫的方法。 提供部分处理半导体晶片，其具有完成了所有金属水平。 在最上层的金属层上形成有覆盖层的介电层。 形成和蚀刻所述电介质层水平和垂直的沟槽阵列形成通过电介质层并将电介质层分离成电池。 沟槽填充有导电材料，并且在执行CMP之后，沉积粘合金属图案。 电线被接合到所述接合金属图案上，之后形成钝化层。

    Novel bonding pad structure to minimize IMD cracking
    5.
    发明申请
    Novel bonding pad structure to minimize IMD cracking 有权
    新型焊盘结构，以尽量减少IMD开裂

    公开(公告)号：US20070035038A1

    公开(公告)日：2007-02-15

    申请号：US11546078

    申请日：2006-10-11

    申请人： Chung Liu ,  Yuan-Lung Liu ,  Ruey-Yun Shiue

    发明人： Chung Liu ,  Yuan-Lung Liu ,  Ruey-Yun Shiue

    IPC分类号： H01L23/48

    CPC分类号： H01L24/05 ,  H01L2224/05093 ,  H01L2224/05094 ,  H01L2224/05095 ,  H01L2224/05096 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/05042 ,  H01L2924/14

    摘要： A method is disclosed of forming a bonding pad that is immune to IMD cracking. A partially processes semiconductor wafer is provided having all metal levels completed. A blanket dielectric layer is formed over the uppermost metal level. Patterning and etching said dielectric layer horizontal and vertical arrays of trenches are formed passing through the dielectric layer and separating the dielectric layer into cells. The trenches are filled with a conducting material and, after performing CMP, bonding metal patterns are deposited. Wires are bonded onto said bonding metal patters, after which a passivation layer is formed.

    摘要翻译： 公开了形成对IMD开裂免疫的接合垫的方法。 提供部分处理半导体晶片，其具有完成了所有金属水平。 在最上层的金属层上形成有覆盖层的介电层。 形成和蚀刻所述电介质层水平和垂直的沟槽阵列形成通过电介质层并将电介质层分离成电池。 沟槽填充有导电材料，并且在执行CMP之后，沉积粘合金属图案。 电线被接合到所述接合金属图案上，之后形成钝化层。

    Bonding pad structure to minimize IMD cracking
    6.
    发明授权
    Bonding pad structure to minimize IMD cracking 有权
    粘合垫结构以最小化IMD开裂

    公开(公告)号：US07135395B2

    公开(公告)日：2006-11-14

    申请号：US10916797

    申请日：2004-08-12

    申请人： Chung Liu ,  Yuan-Lung Liu ,  Ruey-Yun Shiue

    发明人： Chung Liu ,  Yuan-Lung Liu ,  Ruey-Yun Shiue

    IPC分类号： H01L21/44

    CPC分类号： H01L24/05 ,  H01L2224/05093 ,  H01L2224/05094 ,  H01L2224/05095 ,  H01L2224/05096 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/05042 ,  H01L2924/14

    摘要： A method is disclosed of forming a bonding pad that is immune to IMD cracking. A partially processes semiconductor wafer is provided having all metal levels completed. A blanket dielectric layer is formed over the uppermost metal level. Patterning and etching said dielectric layer horizontal and vertical arrays of trenches are formed passing through the dielectric layer and separating the dielectric layer into cells. The trenches are filled with a conducting material and, after performing CMP, bonding metal patterns are deposited. Wires are bonded onto said bonding metal patters, after which a passivation layer is formed.

    摘要翻译： 公开了形成对IMD开裂免疫的接合垫的方法。 提供部分处理半导体晶片，其具有完成了所有金属水平。 在最上层的金属层上形成有覆盖层的介电层。 形成和蚀刻所述电介质层水平和垂直的沟槽阵列形成通过电介质层并将电介质层分离成电池。 沟槽填充有导电材料，并且在执行CMP之后，沉积粘合金属图案。 电线被接合到所述接合金属图案上，之后形成钝化层。