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    Register error protection through binary translation
    1.
    发明授权
    Register error protection through binary translation 有权
    通过二进制转换来注册错误保护

    公开(公告)号：US09405647B2

    公开(公告)日：2016-08-02

    申请号：US13994697

    申请日：2011-12-30

    申请人： Xavier Vera ,  Javier Carretero Casado ,  Matteo Monchiero ,  Tanausu Ramirez ,  Enric Herrero

    发明人： Xavier Vera ,  Javier Carretero Casado ,  Matteo Monchiero ,  Tanausu Ramirez ,  Enric Herrero

    IPC分类号： G06F11/00 ,  G06F11/263 ,  G06F9/45

    CPC分类号： G06F11/263 ,  G06F8/52 ,  G06F9/3013 ,  G06F11/004

    摘要： Some implementations provide techniques and arrangements for detecting a register value having a life longer than a threshold period based, at least in part, on at least one code segment of a code being translated by a binary translator. For a register value detected as having a life longer than a threshold period, at least one instruction to cause an access of the detected register value during the life of the register value may be included in at least one translated code segment to be output by the binary translator.

    摘要翻译： 至少部分地基于由二进制翻译器翻译的代码的至少一个代码段，一些实现提供用于检测具有比阈值周期长的寿命的寄存器值的技术和布置。 对于被检测为寿命长于阈值周期的寄存器值，至少一个在寄存器值的寿命期间使检测到的寄存器值的访问的指令可以包括在至少一个转换的代码段中，以由 二进制翻译器

    Exploiting Frame to Frame Coherency in a Sort-Middle Architecture
    2.
    发明申请
    Exploiting Frame to Frame Coherency in a Sort-Middle Architecture 有权
    在中间架构中利用帧到帧一致性

    公开(公告)号：US20150332429A1

    公开(公告)日：2015-11-19

    申请号：US14277239

    申请日：2014-05-14

    申请人： Juan Fernandez ,  Javier Carretero Casado ,  Pedro Marcuello ,  Tomas G. Akenine-Moller

    发明人： Juan Fernandez ,  Javier Carretero Casado ,  Pedro Marcuello ,  Tomas G. Akenine-Moller

    IPC分类号： G06T1/60 ,  G09G5/36 ,  G06T1/20

    CPC分类号： G06T1/20 ,  G06T1/60 ,  G06T11/40 ,  G06T15/005 ,  G06T17/10 ,  G06T2200/28 ,  G09G5/363 ,  G09G2330/021 ,  G09G2360/122

    摘要： Pixel values that were computed in a previous frame may be reused for the current frame, operating in a sort-middle architecture. A hash or some other compact representation of all the data used in a tile, including all triangles, uniforms, textures, shaders, etc. is computed and stored for each tile. When rendering the next frame, that compact representation is once again computed for each tile. In a sort-middle architecture, there is a natural break point just before rasterization. At this break point, the compact representation may be compared to the compact representation computed in the previous frame for the same tile. If those compact representations are the same, then there is no need to render anything for this tile. Instead, the contents of the color buffer or other buffers of the previous frame of the tile may be moved to the same buffer of the tile for the current frame.

    摘要翻译： 在前一帧中计算的像素值可以重新用于当前帧，以分类中间架构操作。 对于每个瓦片，计算并存储瓦片中使用的所有数据的哈希或其他紧凑表示，包括所有三角形，制服，纹理，着色器等。 在渲染下一帧时，再次对每个图块计算出该紧凑表示。 在一个中间架构中，光栅化之前就有一个自然的断点。 在这个断点处，可以将紧凑表示与在同一瓦片的前一帧中计算的紧凑表示进行比较。 如果这些紧凑的表示是相同的，那么就不需要为这个图块渲染任何东西。 相反，彩色缓冲区或块的先前帧的其他缓冲区的内容可以被移动到当前帧的瓦片的相同缓冲器。

    SELECTIVE PROVISION OF ERROR CORRECTION FOR MEMORY
    3.
    发明申请
    SELECTIVE PROVISION OF ERROR CORRECTION FOR MEMORY 有权
    选择性提供存储器的错误校正

    公开(公告)号：US20140258805A1

    公开(公告)日：2014-09-11

    申请号：US13792117

    申请日：2013-03-10

    申请人： Javier Carretero Casado ,  Xavier Vera ,  Daniel Sanchez ,  Tanausu Ramirez ,  Enric Herrero Abellanas ,  Nicholas Axelos

    发明人： Javier Carretero Casado ,  Xavier Vera ,  Daniel Sanchez ,  Tanausu Ramirez ,  Enric Herrero Abellanas ,  Nicholas Axelos

    IPC分类号： H03M13/35

    CPC分类号： H03M13/35 ,  G06F11/1012

    摘要： Embodiments of apparatuses, methods, and storage medium associated with selectively providing error correction to memory are disclosed herein. In one instance, an apparatus may include a memory controller configured to control access to a non-volatile memory having storage locations. The controller may be configured to provide a first error correction arrangement to provide a first level of error correction capability for data stored in the non-volatile memory. The memory controller may include a control/error correction block configured to provide a second error correction arrangement with a second level of error correction capability for data stored in the non-volatile memory. The second level of error correction capability enables correction of at least one bit error more than the first level. The memory controller may be configured to selectively employ the second error correction arrangement to complement the first error correction arrangement. Other embodiments may be described and claimed.

    摘要翻译： 本文公开了与选择性地向存储器提供错误校正相关联的装置，方法和存储介质的实施例。 在一种情况下，装置可以包括被配置为控制对具有存储位置的非易失性存储器的访问的存储器控​​制器。 控制器可以被配置为提供第一纠错装置，以便为存储在非易失性存储器中的数据提供第一级的纠错能力。 存储器控制器可以包括控制/错误校正块，其被配置为向存储在非易失性存储器中的数据提供具有第二级纠错能力的第二纠错装置。 第二级的纠错能力能够比第一级别更正至少一位误差。 存储器控制器可以被配置为选择性地使用第二纠错装置来补充第一纠错装置。 可以描述和要求保护其他实施例。

    REGISTER ERROR PROTECTION THROUGH BINARY TRANSLATION
    4.
    发明申请
    REGISTER ERROR PROTECTION THROUGH BINARY TRANSLATION 有权
    通过二进制翻译进行注册错误保护

    公开(公告)号：US20130318401A1

    公开(公告)日：2013-11-28

    申请号：US13994697

    申请日：2011-12-30

    申请人： Xavier Vera ,  Javier Carretero Casado ,  Matteo Monchiero ,  Tanausu Ramirez ,  Enric Herrero

    发明人： Xavier Vera ,  Javier Carretero Casado ,  Matteo Monchiero ,  Tanausu Ramirez ,  Enric Herrero

    IPC分类号： G06F11/263

    CPC分类号： G06F11/263 ,  G06F8/52 ,  G06F9/3013 ,  G06F11/004

    摘要： Some implementations provide techniques and arrangements for detecting a register value having a life longer than a threshold period based, at least in part, on at least one code segment of a code being translated by a binary translator. For a register value detected as having a life longer than a threshold period, at least one instruction to cause an access of the detected register value during the life of the register value may be included in at least one translated code segment to be output by the binary translator.

    摘要翻译： 至少部分地基于由二进制翻译器翻译的代码的至少一个代码段，一些实现提供用于检测具有比阈值周期长的寿命的寄存器值的技术和布置。 对于被检测为寿命长于阈值周期的寄存器值，至少一个在寄存器值的寿命期间使检测到的寄存器值的访问的指令可以包括在至少一个转换的代码段中，以由 二进制翻译器

    TRACKING DISTRIBUTED EXECUTION ON ON-CHIP MULTINODE NETWORKS WITHOUT A CENTRALIZED MECHANISM
    9.
    发明申请
    TRACKING DISTRIBUTED EXECUTION ON ON-CHIP MULTINODE NETWORKS WITHOUT A CENTRALIZED MECHANISM 审中-公开
    在没有集中化机制的情况下跟踪片上多线程网络的分布式执行

    公开(公告)号：US20140237018A1

    公开(公告)日：2014-08-21

    申请号：US13993313

    申请日：2011-12-23

    申请人： Matteo Monchiero ,  Javier Carretero Casado ,  Enric Herrero ,  Tanausu Ramirez ,  Xavier Vera

    发明人： Matteo Monchiero ,  Javier Carretero Casado ,  Enric Herrero ,  Tanausu Ramirez ,  Xavier Vera

    IPC分类号： H04L12/24

    CPC分类号： H04L41/046 ,  G06F15/7825

    摘要： A method and system for tracking distributed execution on on-chip multinode networks, the method comprising: initiating, by a first node coupled to an on-chip network, execution of instructions on the first node for a distributed agent; initiating, by the first node, execution of instructions on a second node coupled to the on-chip network for the distributed agent; initiating, by the second node, execution of instructions on a third node coupled to the on-chip network for the distributed agent, wherein the second node does not notify the first node of the initiated execution on the third node; providing reoccurring notification by the second and third nodes to all nodes coupled to the on-chip network that they continue to execute instructions for the distributed agent; and determining, by the first node, that execution of instructions for the distributed agent is complete by detecting an absence of reoccurring notifications from nodes the network.

    摘要翻译： 一种用于跟踪片上多节点网络上的分布式执行的方法和系统，所述方法包括：由耦合到片上网络的第一节点发起用于分布式代理的所述第一节点上的指令的执行; 由所述第一节点发起在耦合到所述分布式代理的片上网络的第二节点上执行指令; 由所述第二节点发起在所述分布式代理上耦合到所述片上网络的第三节点上的指令的执行，其中所述第二节点不在所述第三节点上通知所述第一节点所述发起的执行; 提供由第二和第三节点向连接到片上网络的所有节点重发的通知，他们继续执行分发代理的指令; 以及由所述第一节点通过检测不存在来自所述网络的节点的再发送的通知来确定所述分布式代理的指令的执行是否完成。

    TRAFFIC CONTROL ON AN ON-CHIP NETWORK
    10.
    发明申请
    TRAFFIC CONTROL ON AN ON-CHIP NETWORK 有权
    一个片上网络的交通控制

    公开(公告)号：US20140010079A1

    公开(公告)日：2014-01-09

    申请号：US13993575

    申请日：2011-12-23

    申请人： Matteo Monchiero ,  Javier Carretero Casado ,  Enric Herrero Abellanas ,  Tanausu Ramirez ,  Xavier Vera

    发明人： Matteo Monchiero ,  Javier Carretero Casado ,  Enric Herrero Abellanas ,  Tanausu Ramirez ,  Xavier Vera

    IPC分类号： H04L12/825

    CPC分类号： H04L47/25 ,  G06F15/7825 ,  H04L47/263 ,  Y02D10/12 ,  Y02D10/13 ,  Y02D50/10

    摘要： An apparatus, system, and method for controlling traffic on an on-chip network. Embodiments of the method comprise injecting a packet at a first rate into the on-chip network by a first node coupled to the on-chip network, receiving the packet at a second node coupled to the on-chip network, modifying a bit in the packet by the second node in response to determining that a rate at which packets are injected into the on-chip network should change, returning the packet with the bit modified to the first node by the second node, and changing the first rate by the first node in response to detecting that the bit in the packet was modified.

    摘要翻译： 一种用于控制片上网络上的业务的装置，系统和方法。 该方法的实施例包括通过耦合到片上网络的第一节点将分组以第一速率注入到片上网络，在耦合到片上网络的第二节点处接收分组，修改 响应于确定分组被注入到片上网络的速率应该改变，由第二节点分组，将具有由第二节点修改的比特的分组返回到第一节点，并且将第一速率改变第一节点 响应于检测到分组中的比特被修改。