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公开(公告)号：US07221188B2
公开(公告)日：2007-05-22
申请号：US10967563
申请日：2004-10-18
IPC分类号： H03K19/096
CPC分类号： H03K19/0963
摘要： A logic circuit including at least one evaluate circuit coupled to a static output logic circuit. In one example, the evaluate circuit includes a dynamic node, a full keeper, an evaluate device, and a logic tree. In some examples, the output logic circuit is a sampled static output logic circuit and includes a sample device. In some examples, the logic circuit includes multiple evaluate circuits, each with a dynamic node coupled to a control gate of a transistor of the output logic circuit. Some examples may include a delay in a clock signal to increase the internal race margin.
摘要翻译： 逻辑电路，包括耦合到静态输出逻辑电路的至少一个评估电路。 在一个示例中，评估电路包括动态节点，完整守护者，评估设备和逻辑树。 在一些示例中，输出逻辑电路是采样静态输出逻辑电路，并且包括采样器件。 在一些示例中，逻辑电路包括多个评估电路，每个评估电路具有耦合到输出逻辑电路的晶体管的控制栅极的动态节点。 一些示例可以包括时钟信号的延迟以增加内部游隙。
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公开(公告)号：US5499204A
公开(公告)日：1996-03-12
申请号：US270628
申请日：1994-07-05
CPC分类号： G06F12/0875
摘要： A memory cache (14) has a plurality of cache lines (50) for storing a series of contiguous memory elements. Each series of memory elements are interlaced within the corresponding cache line on a element-by-element basis and on a bit-by-bit basis. This storage strategy allows the memory cache to output a subset memory elements within a cache line quickly and in the original contiguous order. The invention may be advantageously incorporated in an instruction cache of superscalar data processor to provide a series of sequential instructions for execution.
摘要翻译： 存储器高速缓存（14）具有用于存储一系列连续的存储器元件的多个高速缓存行（50）。 每个系列的存储器元件在逐个元件的基础上并且逐位地在相应的高速缓存行内隔行扫描。 该存储策略允许存储器高速缓存在快速和原始的连续顺序内在高速缓存行中输出子集存储器元件。 本发明可以有利地结合在超标量数据处理器的指令高速缓存中，以提供一系列用于执行的顺序指令。
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3.发明授权Method and apparatus for performing integer and floating point division using a single SRT divider in a data processor 失效用于在数据处理器中使用单个SRT分频器执行整数和浮点除法的方法和装置
公开(公告)号：US5272660A
公开(公告)日：1993-12-21
申请号：US891095
申请日：1992-06-01
申请人： Paul C. Rossbach
发明人： Paul C. Rossbach
CPC分类号： G06F7/535 , G06F7/5375 , G06F7/4873
摘要： A method and apparatus for performing integer and floating-point divide operations using a single modified SRT divider in a data processor. The floating-point and integer division is performed using SRT division on normalized positive mantissas (dividend and divisor). Integer division shares portions of the floating point circuitry, however, the sequence of operations is modified during the performance of an integer divide operation. The SRT divider performs a sequence of operations before and after an iteration loop to re-configure an integer divisor and dividend into a data path representation which the SRT algorithm requires for floating-point mantissas. During the iteration loop, quotient bits are selected and used to generate intermediate partial remainders. The quotient bits are also input to quotient registers which accumulate the final quotient mantissa. A full mantissa adder is used to generate a final remainder.
摘要翻译： 一种用于在数据处理器中使用单个修改的SRT分频器执行整数和浮点除法运算的方法和装置。 使用归一化正尾数（股利和除数）的SRT除法执行浮点和整数除法。 整数分割共享浮点电路的部分，然而，在执行整数除法运算期间，操作序列被修改。 SRT分频器在迭代循环之前和之后执行一系列操作，以将整数除数和股息重新配置为SRT算法对浮点尾数所需的数据路径表示。 在迭代循环期间，商位被选择并用于产生中间部分余数。 商位也被输入到累积最终商尾数的商寄存器。 使用全尾数加法器来产生最后的余数。
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4.发明授权In a data processor an SRT divider having a negative divisor sticky detection circuit 失效在数据处理器中，SRT分频器具有负的因数粘性检测电路
公开(公告)号：US5237525A
公开(公告)日：1993-08-17
申请号：US891094
申请日：1992-06-01
申请人： Paul C. Rossbach
发明人： Paul C. Rossbach
CPC分类号： G06F7/535 , G06F7/5375 , G06F7/4873 , G06F7/49952
摘要： In a data processor an Sweeney-Robertson-Tocher (SRT) divider is provided having a negative divisor sticky detection circuit. The negative divisor sticky detection circuit allows negative sticky correction to occur in the SRT divider without requiring additional iteration cycles. At the conclusion of iterative cycles of a divide operation, a final remainder is formed and stored in a latch in the SRT divider. The negative divisor sticky detection circuit determines whether a negative final remainder is equal in magnitude to a divisor value by bit-wise XORing the final remainder with the two's complement value of a divisor, immediately before sticky logic detects the negative sticky bit. The final sticky value is obtained by logically combining the negative sticky bit with a positive sticky bit computed by a positive divisor sticky detection circuit.
摘要翻译： 在一个数据处理器中，提供了一个Sweeney-Robertson-Tocher（SRT）分频器，其具有负的因数粘性检测电路。 负除数粘性检测电路允许在SRT分频器中发生负粘性校正，而不需要额外的迭代循环。 在除法运算的迭代循环结束时，形成最后的余数并将其存储在SRT分频器中的锁存器中。 负除数粘性检测电路在粘性逻辑检测到负粘性位之前，通过逐位异或除数的二进制补码来确定负的最终余数是否与幅度上的等值相等。 最后的粘性值是通过将负粘性位与由正除数粘性检测电路计算的正粘性位逻辑组合而获得的。
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公开(公告)号：US5530824A
公开(公告)日：1996-06-25
申请号：US222779
申请日：1994-04-04
申请人： Chih-Jiu Peng , Paul C. Rossbach
发明人： Chih-Jiu Peng , Paul C. Rossbach
CPC分类号： G06F12/1027 , G06F2212/652
摘要： A CAM/SRAM structure (42) performs address translations of variable length blocks, a "block address translator." Each address translation is stored in a register broken into an upper half and a lower half. The upper half contains CAM bit cells (56) which match an input effective address to a stored tag (BEPI) alternating with SRAM bit cells which store a block length tag (BL). The block length tag defines the length of the translated block and, hence, the number of bits which must match between the input effective address and the stored tag. The lower half contains SRAM bit cells which store a real address associated with the tag (BRPN) alternating with multiplexer circuits. In the event of a CAM match, each multiplexer circuit outputs either a real address bit or an input effective address bit, depending upon the block length tag. The two halves of each register are fabricated adjacent to each other in parallel rows to minimize routing requirements and reduce overall circuit capacitance.
摘要翻译： CAM / SRAM结构（42）执行可变长度块的地址转换，“块地址转换器”。 每个地址转换都存储在一个分成上半部分和下半部分的寄存器中。 上半部包含与存储块长度标签（BL）的SRAM位单元交替的与存储标签（BEPI）匹配的CAM位单元（56）。 块长度标签定义转换块的长度，因此定义输入有效地址和存储标签之间必须匹配的位数。 下半部分包含存储与多路复用器电路交替的与标签（BRPN）相关联的实际地址的SRAM位单元。 在CAM匹配的情况下，每个复用器电路根据块长度标签输出实际地址位或输入有效地址位。 每个寄存器的两半是以并行的方式彼此相邻制造的，以最小化路由要求并降低整体电路电容。
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公开(公告)号：US5291076A
公开(公告)日：1994-03-01
申请号：US937018
申请日：1992-08-31
IPC分类号： G06F7/02 , H03K19/017 , H03K19/096 , H03K19/0948
CPC分类号： G06F7/02 , H03K19/01735 , H03K19/0963
摘要： A precharge device (28) has a first (30) and a second node (32), a transistor tree (29), a screening transistor (Q20) and clocking circuitry (Q17, Q18, Q19). The transistor tree (29) couples the first (30) and the second (32) node and is operable to electrically short-circuit the nodes according to input signals (A.sub.1, A.sub.2, A.sub.3). The screening transistor (Q20) has a first and a second [source-drain region] current electrode and a [gate] control electrode. The first [source-drain region] current electrode is coupled to a third node (34), the second [source-drain region] current electrode is coupled to the second node (32) and the [gate] control electrode is coupled to the first node (30). The clocking circuitry alternately precharges the first (30) and third nodes (34) to a first known voltage level and evaluates the voltage on the first node (30) to output a logic level.
摘要翻译： 预充电装置（28）具有第一（30）和第二节点（32），晶体管树（29），屏蔽晶体管（Q20）和时钟电路（Q17，Q18，Q19）。 晶体管树（29）耦合第一（30）和第二（32）节点，并且可操作以根据输入信号（A1，A2，A3）使节点电短路。 屏蔽晶体管（Q20）具有第一和第二（源极 - 漏极区）电流电极和（栅极）控制电极。 第一（源极 - 漏极区）电流电极耦合到第三节点（34），第二（源极 - 漏极区域）电流电极耦合到第二节点（32），并且（栅极）控制电极耦合到 第一节点（30）。 时钟电路将第一（30）和第三节点（34）交替预充电到第一已知电压电平，并评估第一节点（30）上的电压以输出逻辑电平。
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7.发明授权
公开(公告)号：US6157999A
公开(公告)日：2000-12-05
申请号：US868467
申请日：1997-06-03
CPC分类号： G06F9/3806 , G06F9/30054 , G06F9/3844 , G06F9/4426
摘要： When a request to branch to an address stored in a return memory location (440) occurs, a busy bit is used to determine whether the return memory location (440) contains updated information. When the information is not updated, a predicted address is provided to the prediction verifier (460) by the link stack (410). Once the busy bit is valid, the prediction verifier (460) determines if a proper prediction was made. When an improper prediction was made, the update portion (415) of the link stack (410) based on information from the comparator (425) determines if a value stored in the link stack (410) matches the value stored in the return memory location (440). The link stack (410) is synchronized based upon a favorable comparison indicating the return memory location value matches a value in the link stack. If a match is not found, the predicted address is placed back on the link stack or alternatively the link stack is cleared.
摘要翻译： 当发生分支到存储在返回存储器位置（440）中的地址的请求时，使用忙位来确定返回存储器位置（440）是否包含更新的信息。 当不更新信息时，通过链路栈（410）将预测地址提供给预测验证器（460）。 一旦忙位有效，预测验证器（460）确定是否进行了适当的预测。 当进行不正确的预测时，基于来自比较器（425）的信息，链接堆栈（410）的更新部分（415）确定存储在链接堆栈（410）中的值是否与存储在返回存储器位置中的值相匹配 （440）。 基于指示返回存储器位置值与链路栈中的值匹配的有利比较，链路栈（410）被同步。 如果没有找到匹配项，则将预测的地址放回到链路栈，或者链路栈被清除。
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8.发明授权Data processor with programmable levels of speculative instruction fetching and method of operation 失效数据处理器具有可编程级别的推测指令提取和操作方法
公开(公告)号：US5553255A
公开(公告)日：1996-09-03
申请号：US429439
申请日：1995-04-27
IPC分类号： G06F9/38
CPC分类号： G06F9/3804 , G06F9/3836 , G06F9/384 , G06F9/3844 , G06F9/3846 , G06F9/3857
摘要： A data processor (12) has a branch prediction unit (28) that predicts conditional branch instructions and a control unit (70) therein that monitors the number of unresolved branch instructions. This control unit selectively allows the data processor to fetch the instructions indicated by the branch prediction unit from an external memory system depending upon the number of unresolved branch instructions. The particular threshold number of unresolved branch instructions is user programmable. The data processor thereby limits its bus accesses to those occasions when it is reasonably sure that it will need the indicated instructions.
摘要翻译： 数据处理器（12）具有预测条件分支指令的分支预测单元（28）和其中监视未解决的分支指令的数量的控制单元（70）。 该控制单元选择性地允许数据处理器根据未解决的分支指令的数量从外部存储器系统取出由分支预测单元指示的指令。 未解决的分支指令的特定阈值数量是用户可编程的。 因此，当合理确定需要指示的指令时，数据处理器将其总线访问限制在那些场合。
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9.发明授权Memory cache with automatic alliased entry invalidation and method of operation 失效具有自动多项输入无效的内存缓存和操作方法
公开(公告)号：US5550995A
公开(公告)日：1996-08-27
申请号：US176812
申请日：1994-01-03
CPC分类号： G06F12/1045 , G06F12/0859
摘要： A memory cache (14) has a semi-associative cache array (50), a cache reload buffer (40), and a cache reload buffer driver (42). The memory cache writes received data to the cache reload buffer and waits until the data is requested again before it invalidates any cache aliased entries in the semi-associative cache array. This invalidation step requires no dedicated cycle but instead is a result of the memory cache being able to simultaneously read from the semi-associative cache array and the cache reload buffer.
摘要翻译： 存储器缓存（14）具有半关联高速缓存阵列（50），高速缓存重新加载缓冲器（40）和高速缓存重新加载缓冲器驱动器（42）。 存储器缓存将接收到的数据写入高速缓存重新加载缓冲器，并等待直到在半关联高速缓存阵列中的任何高速缓存别名条目失效之前再次请求数据。 该无效步骤不需要专用周期，而是由存储器缓存能够同时从半关联高速缓存阵列和高速缓存重新加载缓冲器中读取的结果。
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