公开(公告)号：US06989696B2

公开(公告)日：2006-01-24

申请号：US10707066

申请日：2003-11-19

申请人： Rolf Hilgendorf ,  Jens Kuenzer ,  Cédric Lichtenau ,  Thomas Pflueger ,  Mathew I. Ringler ,  Gerard M. Salem ,  Peter A. Sandon ,  Dana J. Thygesen ,  Ulrich Weiss

发明人： Rolf Hilgendorf ,  Jens Kuenzer ,  Cédric Lichtenau ,  Thomas Pflueger ,  Mathew I. Ringler ,  Gerard M. Salem ,  Peter A. Sandon ,  Dana J. Thygesen ,  Ulrich Weiss

IPC分类号： H03L7/00

CPC分类号： H03L7/06

摘要： A synchronization system capable of simultaneously resetting frequency divide-by counters (124A, 124B) of multiple processors (A, B) to zero regardless of the divide-by frequency signal (Mclk/n signal (168A, 168B)) and regardless of the magnitude of the clock mesh delays experienced by the Mclk/n signals in the processors. The synchronization system includes a mesh delay circuit (176A, 176B) for each processor that simulates in the undivided signal (Mclk/1 signal (136A, 136B)) the clock mesh delay experienced by the Mclk/n signal in that processor so as to provide an Lclk signal (172A, 172B). A phase detector detects the phase offset between the Mclk/n signal and the Sysclk signal (112) and sends an asynchronous offset signal (194A, 194B) to a counter re-setter (196A, 196B) that resets the divide-by counter to zero based on the offset signal.

摘要翻译： 能够将多个处理器（A，B）的频率分频计数器（124A，124BB）同时复位的同步系统为零，而不管分频频率 信号（Mclk / n信号（168A，168B）），并且与处理器中的Mclk / n信号经历的时钟网格延迟的大小无关。 同步系统包括用于在未分割信号中模拟的每个处理器的网格延迟电路（176A，176BB）（Mclk / 1信号（136 < / SUB>，136 B））由该处理器中的Mclk / n信号经历的时钟网格延迟，以便提供Lclk信号（172 ，172 _{B ）。 相位检测器检测Mclk / n信号和Sysclk信号之间的相位偏移（112），并将异步偏移信号（194A，192B）发送到计数器 基于偏移信号将再分配计数器复位为零的重新设置器（196A，196BB）。}

公开(公告)号：US20050104637A1

公开(公告)日：2005-05-19

申请号：US10707066

申请日：2003-11-19

申请人： Rolf Hilgendorf ,  Jens Kuenzer ,  Cedric Lichtenau ,  Thomas Pflueger ,  Mathew Ringler ,  Gerard Salem ,  Peter Sandon ,  Dana Thygesen ,  Ulrich Weiss

发明人： Rolf Hilgendorf ,  Jens Kuenzer ,  Cedric Lichtenau ,  Thomas Pflueger ,  Mathew Ringler ,  Gerard Salem ,  Peter Sandon ,  Dana Thygesen ,  Ulrich Weiss

IPC分类号： H03L7/06

CPC分类号： H03L7/06

摘要： A synchronization system capable of simultaneously resetting frequency divide-by counters (124A, 124B) of multiple processors (A, B) to zero regardless of the divide-by frequency signal (Mclk/n signal (168A, 168B)) and regardless of the magnitude of the clock mesh delays experienced by the Mclk/n signals in the processors. The synchronization system includes a mesh delay circuit (176A, 176B) for each processor that simulates in the undivided signal (Mclk/1 signal (136A, 136B)) the clock mesh delay experienced by the Mclk/n signal in that processor so as to provide an Lclk signal (172A, 172B). A phase detector detects the phase offset between the Mclk/n signal and the Sysclk signal (112) and sends an asynchronous offset signal (194A, 194B) to a counter re-setter (196A, 196B) that resets the divide-by counter to zero based on the offset signal.

摘要翻译： 能够将多个处理器（A，B）的频率分频计数器（124A，124BB）同时复位的同步系统为零，而不管分频频率 信号（Mclk / n信号（168A，168B）），并且与处理器中的Mclk / n信号经历的时钟网格延迟的大小无关。 同步系统包括用于在未分割信号中模拟的每个处理器的网格延迟电路（176A，176BB）（Mclk / 1信号（136 < / SUB>，136 B））由该处理器中的Mclk / n信号经历的时钟网格延迟，以便提供Lclk信号（172 ，172 _{B ）。 相位检测器检测Mclk / n信号和Sysclk信号之间的相位偏移（112），并将异步偏移信号（194A，192B）发送到计数器 基于偏移信号将再分配计数器复位为零的重新设置器（196A，196BB）。}

公开(公告)号：US07667504B2

公开(公告)日：2010-02-23

申请号：US12045894

申请日：2008-03-11

申请人： Florian Braun ,  Dedric Lichtenau ,  Thomas Pflueger ,  Ulrich Weiss

发明人： Florian Braun ,  Dedric Lichtenau ,  Thomas Pflueger ,  Ulrich Weiss

IPC分类号： H03B19/00

CPC分类号： H03K5/156 ,  H03K5/135 ,  H03K2005/00052 ,  H03L7/07 ,  H03L7/0814

摘要： The invention relates to frequency adjustment of electronic signals. The method comprises the steps of providing an output signal of a frequency generator with a first frequency as input signal for a signal delay element providing an edge of said input signal of said signal delay element; delaying said input signal by adding a delay to each cycle of said input signal until the delayed output signal of the signal delay element is aligned to an edge of said input signal.

摘要翻译： 本发明涉及电子信号的频率调整。 该方法包括以下步骤：提供具有第一频率的频率发生器的输出信号作为提供所述信号延迟元件的所述输入信号的边沿的信号延迟元件的输入信号; 通过向所述输入信号的每个周期添加延迟来延迟所述输入信号，直到信号延迟元件的延迟的输出信号与所述输入信号的边沿对准。

公开(公告)号：US20090021288A1

公开(公告)日：2009-01-22

申请号：US12045894

申请日：2008-03-11

申请人： Florian Braun ,  Cedric Lichtenau ,  Thomas Pflueger ,  Ulrich Weiss

发明人： Florian Braun ,  Cedric Lichtenau ,  Thomas Pflueger ,  Ulrich Weiss

IPC分类号： H03B19/00

CPC分类号： H03K5/156 ,  H03K5/135 ,  H03K2005/00052 ,  H03L7/07 ,  H03L7/0814

摘要： The invention relates to frequency adjustment of electronic signals. The method comprises the steps of providing an output signal of a frequency generator with a first frequency as input signal for a signal delay element providing an edge of said input signal of said signal delay element; delaying said input signal by adding a delay to each cycle of said input signal until the delayed output signal of the signal delay element is aligned to an edge of said input signal.

摘要翻译： 本发明涉及电子信号的频率调整。 该方法包括以下步骤：提供具有第一频率的频率发生器的输出信号作为提供所述信号延迟元件的所述输入信号的边沿的信号延迟元件的输入信号; 通过向所述输入信号的每个周期添加延迟来延迟所述输入信号，直到信号延迟元件的延迟的输出信号与所述输入信号的边沿对准。

公开(公告)号：US07260494B2

公开(公告)日：2007-08-21

申请号：US11055829

申请日：2005-02-11

申请人： Ulrich Weiss

发明人： Ulrich Weiss

IPC分类号： G01R31/04

CPC分类号： G01R31/2853 ,  G01R31/31717

摘要： A method, apparatus, and computer program product in a data processing system for testing differential clock or oscillator signals. A method is comprised of the following steps: A first single-ended receiver is connected to a positive leg of a differential pair, and a second single-ended receiver is connected to a negative leg of the differential pair. An output of the first single-ended receiver is inverted and delayed before being input into a first RS Flip-Flop. An output of the second single-ended receiver is delayed before being input into a second RS Flip-Flop. An output of a differential receiver is inverted and input into the first and second RS Flip Flops as reset signals. Then a Wire OK signal is output indicating the condition of the legs of the differential pair.

摘要翻译： 用于测试差分时钟或振荡器信号的数据处理系统中的方法，装置和计算机程序产品。 一种方法包括以下步骤：第一单端接收器连接到差分对的正极，而第二单端接收器连接到差分对的负极。 在输入到第一RS触发器之前，第一单端接收器的输出被反相和延迟。 第二单端接收器的输出在被输入到第二RS触发器之前被延迟。 差分接收器的输出被反相并作为复位信号输入到第一和第二RS触发器。 然后输出一条Wire OK信号，指示差动对的支脚状态。

公开(公告)号：US20060143896A1

公开(公告)日：2006-07-06

申请号：US10800544

申请日：2004-03-15

申请人： Matthew Zaluzec ,  David Cook ,  Ulrich Weiss ,  Maik Broda ,  Clemens Verpoort

发明人： Matthew Zaluzec ,  David Cook ,  Ulrich Weiss ,  Maik Broda ,  Clemens Verpoort

IPC分类号： B21B1/46

CPC分类号： B22D19/0009 ,  B22D19/0081 ,  B22D19/08 ,  C23C2/02 ,  C23C4/18 ,  C23C6/00 ,  F01L3/04 ,  F01L2101/00 ,  F01L2103/00 ,  Y10T29/49231 ,  Y10T29/49984

摘要： A method of manufacturing metallic components consisting of at least two different materials, one of them being an iron-based alloy and the other an aluminum-based alloy, and involving the steps of: depositing a metallic layer onto the body made from the iron-based alloy, said layer being an aluminum-based alloy, preferably based on Al—Si or Fe, placing the coated body in a casting mold and casting an aluminum-based alloy about the coated body. Prior to placing the body in the casting mold, the metallic layer of the body is sprayed and/or blasted with silicon powder and/or Borax (Na2B4O7—10H2O, hydrated sodium borate).

摘要翻译： 一种制造由至少两种不同材料组成的金属组件的方法，其中一种是铁基合金，另一种是铝基合金，包括以下步骤：将金属层沉积在由铁 - 所述层是铝基合金，优选基于Al-Si或Fe，将涂覆体放置在铸模中并且在涂覆体周围浇铸铝基合金。 在将本体放置在铸模中之前，用硅粉和/或硼砂（Na 2 B 4 O 4）喷射和/或喷射身体的金属层， N 2，水合硼酸钠）。

公开(公告)号：US20120117524A1

公开(公告)日：2012-05-10

申请号：US12940762

申请日：2010-11-05

申请人： Friedhelm Kessler ,  Thomas M. Makowski ,  Harald Mielich ,  Ulrich Weiss

发明人： Friedhelm Kessler ,  Thomas M. Makowski ,  Harald Mielich ,  Ulrich Weiss

IPC分类号： G06F17/50

CPC分类号： G06F17/5045

摘要： A method includes removing a code segment from a hardware description language design to create a modified hardware description language design. The code segment represents at least one time sensitive path in the hardware description language design. The method includes creating a delta list of differences between the modified hardware description language design and a physical hardware representation that is logically equivalent to the hardware description language design. The method includes extracting a portion of the physical hardware representation that corresponds to the time sensitive path based, at least in part, on the delta list. The method also includes creating a structured hardware description language design of the time sensitive path using the extracted portion of the physical hardware representation, wherein the structured hardware description language design comprises structural information of the extracted portion of the physical hardware representation.

摘要翻译： 一种方法包括从硬件描述语言设计中移除代码段以创建修改的硬件描述语言设计。 代码段表示硬件描述语言设计中至少一个时间敏感的路径。 该方法包括创建经修改的硬件描述语言设计与在逻辑上等同于硬件描述语言设计的物理硬件表示之间的差异的增量列表。 该方法包括至少部分地基于增量列表提取对应于时间敏感路径的物理硬件表示的一部分。 该方法还包括使用所提取的物理硬件表示的部分来创建时间敏感路径的结构化硬件描述语言设计，其中所述结构化硬件描述语言设计包括所提取的所述物理硬件表示部分的结构信息。

公开(公告)号：US20080294706A1

公开(公告)日：2008-11-27

申请号：US12099973

申请日：2008-04-09

申请人： Wilhelm Haller ,  Rolf Sautter ,  Christoph Wandel ,  Ulrich Weiss

发明人： Wilhelm Haller ,  Rolf Sautter ,  Christoph Wandel ,  Ulrich Weiss

IPC分类号： G06F17/10 ,  G06F7/575

CPC分类号： H03K19/0941 ,  H03K19/0008

摘要： A digital adder circuit comprising a plurality of logical stages in the carry logic of said adder circuit, for generating and propagating predetermined groups of operand bits, each stage implementing a predetermined logic function and processing input variables from a preceding stage and outputting result values to a succeeding stage static and dynamic logic in the carry network of a 4-bit adder, and with output from the first stage fed directly as an input (60, 62) to the third stage of the carry network. Preferably, stages having normally relatively high switching activities are implemented in static logic. Preferably, the first stage of its carry network is implemented in a static logic, and the rest of the stages in dynamic logic.

摘要翻译： 一种数字加法器电路，包括在所述加法器电路的进位逻辑中的多个逻辑级，用于产生和传播预定的操作数位组，每个级实现预定的逻辑功能，并处理来自前一级的输入变量，并将结果值输出到 4位加法器的进位网络中的后级静态和动态逻辑，并且来自第一级的输出直接作为输入（60,62）馈送到进位网络的第三级。 优选地，具有通常相对较高切换活动的阶段在静态逻辑中实现。 优选地，其进位网络的第一级是以静态逻辑实现的，其余的级在动态逻辑中。

公开(公告)号：US20080215906A1

公开(公告)日：2008-09-04

申请号：US12116652

申请日：2008-05-07

申请人： Scott Barnett Swaney ,  Kenneth Lundy Ward ,  Tobias Webel ,  Ulrich Weiss ,  Matthias Woehrle

发明人： Scott Barnett Swaney ,  Kenneth Lundy Ward ,  Tobias Webel ,  Ulrich Weiss ,  Matthias Woehrle

IPC分类号： G06F1/12

CPC分类号： G06F11/1604 ,  G06F1/14 ,  G06F11/20

摘要： Redundant time-of-day (TOD) oscillators are aligned, within a master oscillator path, to local logic oscillator and used to create independent step-sync signals. A step checker validates and provides selection signals to identify which of the TOD oscillators operates according to a criterion. Independent step-sync signals are transmitted to several sibling chips. Local step and sync signals are delayed to arrive at TOD register nearly synchronous with TOD registers in sibling chips. A slave oscillator path may be used to select time signals generated in a sibling chip, whereby the master oscillator path is deselected. A primary control register set may be used to configure which among several chips is a master chip using the master oscillator path. All remaining chips are slave chips. All segments of the topology are redundant. One of multiple possible alternate topologies is defined in a secondary control register set. Commands and TOD values are passed on the fabric at predefined time increment boundaries to establish, restore, or maintain synchronization across all chips.

摘要翻译： 冗余时钟（TOD）振荡器在主振荡器路径内对准本地逻辑振荡器，并用于创建独立的步进同步信号。 步骤检验器验证并提供选择信号，以根据标准识别哪个TOD振荡器工作。 独立的步进同步信号被传送到几个同级芯片。 本地步进和同步信号被延迟到TOD寄存器，与同步芯片中的TOD寄存器几乎同步。 可以使用从属振荡器路径来选择在同级芯片中产生的时间信号，由此主振荡器路径被取消选择。 主控制寄存器组可以用于使用主振荡器路径来配置几个芯片中的哪一个是主芯片。 所有剩余的芯片都是从芯片。 拓扑的所有段都是冗余的。 多个可能的替代拓扑中的一个在二次控制寄存器集中被定义。 命令和TOD值以预定义的时间增量边界在结构上传递，以建立，恢复或维持所有芯片之间的同步。

公开(公告)号：US20050138103A1

公开(公告)日：2005-06-23

申请号：US10973365

申请日：2004-10-26

申请人： Wilhelm Haller ,  Rolf Sautter ,  Christoph Wandel ,  Ulrich Weiss

发明人： Wilhelm Haller ,  Rolf Sautter ,  Christoph Wandel ,  Ulrich Weiss

IPC分类号： G06F7/50 ,  G06F7/506 ,  G06F7/508 ,  H03K19/094

CPC分类号： G06F7/506 ,  G06F7/508 ,  G06F2207/3872 ,  H03K19/0941

摘要： The present invention relates to computer processors. In particular it relates to a method and respective system for operating a digital adder circuit comprising a plurality of logical stages in the carry logic of said adder circuit, for generating and propagating predetermined groups of operand bits, each stage implementing a predetermined logic function and processing input variables from a preceding stage and outputting result values to a succeeding stage. In order to reduce power consumption of adders and concurrently increasing adder speed it is proposed to implement a mixture of static and dynamic logic in the carry network of a 4-bit adder, and to feed output from the first stage directly as an input (60, 62) to the third stage of the carry network. Preferably, stages having normally relatively high switching activities are implemented in static logic. Preferably, the first stage of its carry network is implemented in a static logic, and the rest of the stages in dynamic logic.

摘要翻译： 本发明涉及计算机处理器。 具体地说，涉及用于操作数字加法器电路的方法和相应系统，该数字加法器电路包括在所述加法器电路的进位逻辑中的多个逻辑级，用于产生和传播预定的操作数组组，每个级实现预定的逻辑功能和处理 来自前一级的输入变量并将结果值输出到后一级。 为了降低加法器的功耗并同时增加加法器速度，提出在4位加法器的进位网络中实现静态和动态逻辑的混合，并将第一级的输出直接作为输入（60 ，62）到进位网络的第三阶段。 优选地，具有通常相对较高切换活动的阶段在静态逻辑中实现。 优选地，其进位网络的第一级是以静态逻辑实现的，其余的级在动态逻辑中。