公开(公告)号：US09099199B2

公开(公告)日：2015-08-04

申请号：US13420931

申请日：2012-03-15

申请人： Tzu-Kuei Lin ,  Hung-Jen Liao ,  Jhon Jhy Liaw ,  Yen-Huei Chen

发明人： Tzu-Kuei Lin ,  Hung-Jen Liao ,  Jhon Jhy Liaw ,  Yen-Huei Chen

IPC分类号： G11C11/00 ,  G11C11/412

CPC分类号： G11C11/41 ,  G11C11/412

摘要： A memory cell includes a first, second, and third columns of devices. The first column of devices includes a first pull-down transistor, a second pull-down transistor, a first switch, and a second switch. The second column of devices includes a third pull-down transistor, a fourth pull-down transistor, a third switch, and a fourth switch. The third column of devices includes a first pull-up transistor, and a second pull-up transistor. The first pull-up transistor, the first pull-down transistor, and the third pull-down transistor are connected as a first inverter, and the second pull-up transistor, the second pull-down transistor, and the fourth pull-down transistor are connected as a second inverter. The first inverter and the second inverter are cross-coupled. The first switch, the second switch, the third switch, and the fourth switch are coupled with output terminals of the first and second inverters.

摘要翻译： 存储器单元包括第一，第二和第三列器件。 第一列器件包括第一下拉晶体管，第二下拉晶体管，第一开关和第二开关。 第二列器件包括第三下拉晶体管，第四下拉晶体管，第三开关和第四开关。 第三列器件包括第一上拉晶体管和第二上拉晶体管。 第一上拉晶体管，第一下拉晶体管和第三下拉晶体管作为第一反相器连接，第二上拉晶体管，第二下拉晶体管和第四下拉晶体管 作为第二反相器连接。 第一个反相器和第二个反相器是交叉耦合的。 第一开关，第二开关，第三开关和第四开关与第一和第二逆变器的输出端子耦合。

公开(公告)号：US08987831B2

公开(公告)日：2015-03-24

申请号：US13349349

申请日：2012-01-12

申请人： Jhon-Jhy Liaw

发明人： Jhon-Jhy Liaw

IPC分类号： H01L27/11 ,  G11C11/412 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/02 ,  H01L27/088 ,  H01L27/12

CPC分类号： H01L27/1104 ,  G11C11/412 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/1108 ,  H01L27/1211

摘要： Static random access memory (SRAM) cells and SRAM cell arrays are disclosed. In one embodiment, an SRAM cell includes a pull-up transistor. The pull-up transistor includes a Fin field effect transistor (FinFET) that has a fin of semiconductive material. An active region is disposed within the fin. A contact is disposed over the active region of the pull-up transistor. The contact is a slot contact that is disposed in a first direction. The active region of the pull-up transistor is disposed in a second direction. The second direction is non-perpendicular to the first direction.

摘要翻译： 公开了静态随机存取存储器（SRAM）单元和SRAM单元阵列。 在一个实施例中，SRAM单元包括上拉晶体管。 上拉晶体管包括具有半导体材料鳍的Fin场效应晶体管（FinFET）。 有源区域设置在翅片内。 触点设置在上拉晶体管的有源区上。 触点是沿第一方向设置的槽接触件。 上拉晶体管的有源区域设置在第二方向。 第二方向与第一方向非垂直。

公开(公告)号：US08952547B2

公开(公告)日：2015-02-10

申请号：US11775039

申请日：2007-07-09

申请人： Jhon-Jhy Liaw

发明人： Jhon-Jhy Liaw

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L27/11 ,  H01L23/522 ,  H01L23/528 ,  H01L23/485 ,  H01L27/02

CPC分类号： H01L27/088 ,  H01L21/32115 ,  H01L21/768 ,  H01L21/76895 ,  H01L21/823425 ,  H01L21/823437 ,  H01L21/823475 ,  H01L23/485 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L27/0207 ,  H01L27/11 ,  H01L27/1104 ,  H01L29/0649 ,  H01L29/66568 ,  H01L2924/0002 ,  H01L2924/00

摘要： A contact structure includes a first contact formed in a first dielectric layer connecting to the source/drain region of a MOS transistor, and a second contact formed in a second dielectric layer connecting to a gate region of a MOS transistor or to a first contact. A butted contact structure abutting a source/drain region and a gate electrode includes a first contact formed in a first dielectric layer connecting to the source/drain region of a MOS transistor, and a second contact formed in a second dielectric layer with one end resting on the gate electrode and the other end in contact with the first contact.

摘要翻译： 接触结构包括形成在连接到MOS晶体管的源极/漏极区域的第一电介质层中的第一接触和形成在连接到MOS晶体管的栅极区域或第一接触点的第二介电层中的第二接触。 邻接源极/漏极区域和栅电极的对接接触结构包括形成在连接到MOS晶体管的源极/漏极区域的第一电介质层中的第一接触和形成在第二电介质层中的第二接触，其一端静止 在栅电极上，另一端与第一触点接触。

公开(公告)号：US20130258759A1

公开(公告)日：2013-10-03

申请号：US13436149

申请日：2012-03-30

申请人： Jhon-Jhy Liaw

发明人： Jhon-Jhy Liaw

IPC分类号： G11C11/00 ,  H01L21/66

CPC分类号： H01L27/1104 ,  G06F17/5072 ,  G06F17/5077 ,  G06F17/5081 ,  G11C11/412 ,  H01L27/0207 ,  H01L27/0924 ,  H01L27/11

摘要： An SRAM cell structure. In one embodiment, a bit cell first level contacts formed at a first and a second CVdd node, a first and a second CVss node, at a bit line node, at a bit line bar node, at a data node and at a data bar node; and second level contacts formed on each of the first level contacts at the first and second CVdd nodes, the first and second CVss nodes, the bit line node and the bit line bar node; wherein the first level contacts formed at the data node and the data bar node do not have a second level contact formed thereon. In another embodiment, a word line is formed and bit lines and a CVdd and a CVss line are formed overlying the SRAM cell and coupled to the corresponding ones of the nodes. Methods are disclosed for forming the cell structure.

公开(公告)号：US20130242644A1

公开(公告)日：2013-09-19

申请号：US13420931

申请日：2012-03-15

申请人： Tzu-Kuei LIN ,  Hung-Jen LIAO ,  Jhon Jhy LIAW ,  Yen-Huei CHEN

发明人： Tzu-Kuei LIN ,  Hung-Jen LIAO ,  Jhon Jhy LIAW ,  Yen-Huei CHEN

IPC分类号： G11C11/40

CPC分类号： G11C11/41 ,  G11C11/412

摘要： A memory cell includes a first, second, and third columns of devices. The first column of devices includes a first pull-down transistor, a second pull-down transistor, a first switch, and a second switch. The second column of devices includes a third pull-down transistor, a fourth pull-down transistor, a third switch, and a fourth switch. The third column of devices includes a first pull-up transistor, and a second pull-up transistor. The first pull-up transistor, the first pull-down transistor, and the third pull-down transistor are connected as a first inverter, and the second pull-up transistor, the second pull-down transistor, and the fourth pull-down transistor are connected as a second inverter. The first inverter and the second inverter are cross-coupled. The first switch, the second switch, the third switch, and the fourth switch are coupled with output terminals of the first and second inverters.

摘要翻译： 存储器单元包括第一，第二和第三列器件。 第一列器件包括第一下拉晶体管，第二下拉晶体管，第一开关和第二开关。 第二列器件包括第三下拉晶体管，第四下拉晶体管，第三开关和第四开关。 第三列器件包括第一上拉晶体管和第二上拉晶体管。 第一上拉晶体管，第一下拉晶体管和第三下拉晶体管作为第一反相器连接，第二上拉晶体管，第二下拉晶体管和第四下拉晶体管 作为第二反相器连接。 第一个反相器和第二个反相器是交叉耦合的。 第一开关，第二开关，第三开关和第四开关与第一和第二逆变器的输出端子耦合。

公开(公告)号：US20130181297A1

公开(公告)日：2013-07-18

申请号：US13349349

申请日：2012-01-12

申请人： Jhon-Jhy Liaw

发明人： Jhon-Jhy Liaw

IPC分类号： H01L27/11

CPC分类号： H01L27/1104 ,  G11C11/412 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/1108 ,  H01L27/1211

摘要： Static random access memory (SRAM) cells and SRAM cell arrays are disclosed. In one embodiment, an SRAM cell includes a pull-up transistor. The pull-up transistor includes a Fin field effect transistor (FinFET) that has a fin of semiconductive material. An active region is disposed within the fin. A contact is disposed over the active region of the pull-up transistor. The contact is a slot contact that is disposed in a first direction. The active region of the pull-up transistor is disposed in a second direction. The second direction is non-perpendicular to the first direction.

摘要翻译： 公开了静态随机存取存储器（SRAM）单元和SRAM单元阵列。 在一个实施例中，SRAM单元包括上拉晶体管。 上拉晶体管包括具有半导体材料鳍的Fin场效应晶体管（FinFET）。 有源区域设置在翅片内。 触点设置在上拉晶体管的有源区上。 触点是沿第一方向设置的槽接触件。 上拉晶体管的有源区域设置在第二方向。 第二方向与第一方向非垂直。

公开(公告)号：US08436405B2

公开(公告)日：2013-05-07

申请号：US13471726

申请日：2012-05-15

申请人： Jhon Jhy Liaw

发明人： Jhon Jhy Liaw

IPC分类号： H01L31/062

CPC分类号： H01L27/11226 ,  G11C17/12 ,  H01L27/0207

摘要： The present disclosure provides a read only memory (ROM) cell array. The ROM cell array includes a plurality of fin active regions oriented in a first direction and formed on a semiconductor substrate; a plurality of gates formed on the plurality of fin active regions and oriented in a second direction perpendicular to the first direction; and a plurality of ROM cells formed by the plurality of fin active regions and the plurality of gates, the plurality of ROM cells being coded such that each cell of a first subset of ROM cells has a source electrically connected to a power line, and each cell of a second subset of ROM cells has a source electrically isolated.

摘要翻译： 本公开提供了只读存储器（ROM）单元阵列。 ROM单元阵列包括在第一方向上取向并形成在半导体衬底上的多个翅片有源区; 形成在所述多个翅片活动区域上的多个栅极，并且在垂直于所述第一方向的第二方向上取向; 以及由多个鳍活动区域和多个栅极形成的多个ROM单元，所述多个ROM单元被编码为使得ROM单元的第一子集的每个单元具有电连接到电力线的源，并且每个 ROM单元的第二子集的单元具有电隔离的源。

公开(公告)号：US08315084B2

公开(公告)日：2012-11-20

申请号：US12721476

申请日：2010-03-10

申请人： Jhon Jhy Liaw ,  Chih-Hung Hsieh

发明人： Jhon Jhy Liaw ,  Chih-Hung Hsieh

IPC分类号： G11C11/00

CPC分类号： G11C11/412 ,  G11C11/413

摘要： The present disclosure provides a dual port static random access memory (SRAM) cell. The dual-port SRAM cell includes four sets of cascaded n-type metal-oxide-semiconductor field-effect transistors (NMOSFETs), each set of cascaded NMOSFETs having a pull-down device and a pass-gate device; and a first and second pull-up devices (PU1 and PU2) configured with the four pull-down devices to form two cross-coupled inverters, wherein two of the pass-gate devices are configured to form a first port and another two of the pass-gate devices are configured to form a second port.

摘要翻译： 本公开提供了一种双端口静态随机存取存储器（SRAM）单元。 双端口SRAM单元包括四组级联的n型金属氧化物半导体场效应晶体管（NMOSFET），每组级联NMOSFET具有下拉装置和通过栅极装置; 以及配置有四个下拉装置以形成两个交叉耦合的反相器的第一和第二上拉装置（PU1和PU2），其中两个通过栅极装置被配置为形成第一端口，另外两个 通路设备被配置为形成第二端口。

公开(公告)号：US20120149171A1

公开(公告)日：2012-06-14

申请号：US13399488

申请日：2012-02-17

申请人： Jhon-Jhy Liaw ,  Chao-Cheng Chen ,  Chia-Wei Chang

发明人： Jhon-Jhy Liaw ,  Chao-Cheng Chen ,  Chia-Wei Chang

IPC分类号： H01L21/762

CPC分类号： H01L21/823878 ,  H01L21/76232

摘要： A shallow trench isolation (STI) structure and methods of forming a STI structure are disclosed. An embodiment is a method for forming a semiconductor structure. The method includes forming a recess in a semiconductor substrate; forming a first material on sidewalls of the recess; forming a widened recessed portion through a bottom surface of the recess; removing the first material from the sidewalls of the recess; and forming a dielectric material in the recess and the widened recessed portion. The bottom surface of the recess is exposed through the first material, and the bottom surface of the recess has a first width. The widened recessed portion has a second width. The second width is greater than the first width.

摘要翻译： 公开了浅沟槽隔离（STI）结构和形成STI结构的方法。 实施例是形成半导体结构的方法。 该方法包括在半导体衬底中形成凹陷; 在所述凹部的侧壁上形成第一材料; 通过所述凹部的底面形成加宽的凹部; 从所述凹部的侧壁去除所述第一材料; 以及在所述凹部和所述加宽的凹部中形成介电材料。 凹部的底面通过第一材料露出，凹部的底面具有第一宽度。 加宽的凹部具有第二宽度。 第二宽度大于第一宽度。

公开(公告)号：US08174868B2

公开(公告)日：2012-05-08

申请号：US12689372

申请日：2010-01-19

申请人： Jhon Jhy Liaw

发明人： Jhon Jhy Liaw

IPC分类号： G11C11/40

CPC分类号： G11C8/16 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1116

摘要： An embedded SRAM chip in a 32 nm or smaller technology generation includes a first SRAM array of first SRAM unit cells. Each first SRAM unit cell includes a data latch for data storage and at least two pass gates for data reading and writing access. The cell area is defined by a first X-pitch and a first Y-pitch, the X-pitch being longer than the Y-pitch. A plurality of logic transistors are formed outside of the first SRAM array, the plurality of logic transistors including at least first and second logic transistor having first and second gate pitches defined between their source and drain contacts. The second gate pitch is the minimum logic gate pitch for the plurality of logic transistors. The first Y-pitch is equal to twice the first gate pitch and the ratio of the first Y-pitch to twice the second logic gate pitch is greater than one.

摘要翻译： 32nm或更小的技术生产中的嵌入式SRAM芯片包括第一SRAM单元单元的第一SRAM阵列。 每个第一SRAM单元包括用于数据存储的数据锁存器和用于数据读取和写入访问的至少两个通过门。 单元区域由第一X间距和第一Y间距限定，X间距长于Y间距。 多个逻辑晶体管形成在第一SRAM阵列的外部，多个逻辑晶体管至少包括第一和第二逻辑晶体管，其中第一和第二逻辑晶体管具有限定在它们的源极和漏极触点之间的第一和第二栅极间距。 第二栅极间距是多个逻辑晶体管的最小逻辑门间距。 第一Y间距等于第一栅极间距的两倍，并且第一Y间距与第二逻辑门间距的两倍之比大于1。