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42 条记录 (耗时 0.018 秒)

    Nonvolatile memory device and method for operating the same
    2.
    发明授权
    Nonvolatile memory device and method for operating the same 有权
    非易失性存储器件及其操作方法

    公开(公告)号：US08677053B2

    公开(公告)日：2014-03-18

    申请号：US12488616

    申请日：2009-06-22

    申请人： Ji-Hyae Bae ,  Kyoung-Wook Park

    发明人： Ji-Hyae Bae ,  Kyoung-Wook Park

    IPC分类号： G06F12/02

    CPC分类号： G11C16/32

    摘要： A nonvolatile memory device includes a selecting unit configured to select one of a read data or a program signal indicating a program period, an output unit configured to output an output signal of the selecting unit to the outside of a chip, and an output pin connected to the output unit.

    摘要翻译： 非易失性存储器件包括：选择单元，被配置为选择读取数据或表示程序周期的程序信号中的一个;输出单元，被配置为将选择单元的输出信号输出到芯片的外部;以及输出引脚连接 到输出单元。

    Device for controlling lock state of block in a semiconductor memory and method for controlling the same
    3.
    发明授权
    Device for controlling lock state of block in a semiconductor memory and method for controlling the same 有权
    用于控制半导体存储器中的块的锁定状态的装置及其控制方法

    公开(公告)号：US08503239B2

    公开(公告)日：2013-08-06

    申请号：US12980267

    申请日：2010-12-28

    申请人： Jung Mi Tak ,  Ji Hyae Bae

    发明人： Jung Mi Tak ,  Ji Hyae Bae

    IPC分类号： G06F12/00 ,  G06F13/00

    CPC分类号： G11C8/12 ,  G11C16/08

    摘要： A block control device for a semiconductor memory and a method for controlling the same are disclosed, which relate to a technology for controlling a block operation state of a Low Power Double-Data-Rate 2 (LPDDR2) non-volatile memory device. A block control device for use in a semiconductor memory includes a block address comparator configured to compare a first block address with a last block address, and output a same pulse or unequal pulse according to the comparison result, a block address driver configured to output a lock state control signal for driving a block address in response to the same pulse, a block address counter configured to count block addresses from the first block address to the last block address in response to the unequal pulse, and generate a block data activation pulse, and a block address register configured to store a lock state of a corresponding block in response to the lock state control signal and the block data activation pulse.

    摘要翻译： 公开了一种用于半导体存储器的块控制装置及其控制方法，其涉及用于控制低功率双数据速率2（LPDDR2）非易失性存储器件的块操作状态的技术。 一种用于半导体存储器的块控制装置，包括块地址比较器，被配置为将第一块地址与最后块地址进行比较，并根据比较结果输出相同的脉冲或不相等的脉冲;块地址驱动器，被配置为输出 锁定状态控制信号，用于响应于相同的脉冲驱动块地址;块地址计数器，被配置为响应于不等脉冲将块地址从第一块地址计数到最后块地址，并且生成块数据激活脉冲， 以及块地址寄存器，被配置为响应于锁定状态控制信号和块数据激活脉冲而存储相应块的锁定状态。

    Semiconductor memory device and method for operating the same
    4.
    发明授权
    Semiconductor memory device and method for operating the same 有权
    半导体存储器件及其操作方法

    公开(公告)号：US08238186B2

    公开(公告)日：2012-08-07

    申请号：US12613347

    申请日：2009-11-05

    申请人： Ji-Hyae Bae ,  Sang-Sie Yoon

    发明人： Ji-Hyae Bae ,  Sang-Sie Yoon

    IPC分类号： G11C7/00

    CPC分类号： G11C7/1006 ,  G11C7/1045 ,  G11C2207/107

    摘要： A semiconductor memory device is capable of performing a stable high-speed operation while inputting/outputting data. The semiconductor memory device includes an inversion output circuit configured to output a clocking pattern in a clocking mode, and an inversion pin to which the inversion output circuit is connected.

    摘要翻译： 半导体存储器件能够在输入/输出数据时执行稳定的高速操作。 半导体存储器件包括反相输出电路，被配置为以时钟模式输出时钟模式，反相输出电路被连接到反相输出电路。

    Semiconductor Memory Device and Operating Method Thereof
    5.
    发明申请
    Semiconductor Memory Device and Operating Method Thereof 失效
    半导体存储器件及其操作方法

    公开(公告)号：US20100277994A1

    公开(公告)日：2010-11-04

    申请号：US12488011

    申请日：2009-06-19

    申请人： Ji-Hyae Bae

    发明人： Ji-Hyae Bae

    IPC分类号： G11C7/00 ,  G11C8/18

    CPC分类号： G11C7/1078 ,  G11C7/109 ,  G11C7/22

    摘要： A semiconductor memory device and an operating method thereof prevent the mal-operation of the semiconductor memory device induced by misrecognizing addresses or data as commands. The semiconductor memory device includes a plurality of input pads, a data information path, a command path, a transfer block configured to transmit signals coupled through the input pads to the data information path and the command path, a command decoding block configured to decode signals transmitted through the command path to verify an inputting of a command, and a transmission control block configured to generate a control signal for controlling the signal transmission from the transfer block to the command path according to the verified result of the command decoding block.

    摘要翻译： 半导体存储器件及其操作方法防止由误认识地址或数据引起的半导体存储器件的误操作作为命令。 半导体存储器件包括多个输入焊盘，数据信息路径，命令路径，被配置为将通过输入焊盘耦合的信号传输到数据信息路径和命令路径的传输块，配置为对信号进行解码的命令解码块 通过命令路径发送以验证命令的输入;以及传输控制块，被配置为根据命令解码块的验证结果产生用于控制从传送块到命令路径的信号传输的控制信号。

    DATA TRANSFER CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME
    6.
    发明申请
    DATA TRANSFER CIRCUIT AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SAME 有权
    数据传输电路和包括其的半导体存储器件

    公开(公告)号：US20090322770A1

    公开(公告)日：2009-12-31

    申请号：US12326985

    申请日：2008-12-03

    申请人： Ji-Hyae Bae

    发明人： Ji-Hyae Bae

    IPC分类号： G06T1/00

    CPC分类号： G11C8/18 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/109 ,  G11C7/1093 ,  G11C29/028 ,  G11C29/12015 ,  G11C29/50 ,  G11C29/50012 ,  G11C2207/2254

    摘要： A data transfer circuit has a reduced number of lines for transferring a training pattern used in a read training for high speed operation, by removing a register for temporarily storing the training pattern, and a semiconductor memory device including the data transfer circuit. The data transfer circuit includes a latch unit and a buffer unit. The latch unit latches one bit of a training pattern data input together with a training pattern load command whenever the training pattern load command is input. The buffer unit loads a plurality of bits latched in the latch unit, including the one bit of training pattern data, in response to a strobe signal.

    摘要翻译： 数据传输电路具有用于传送用于高速操作的读取训练中使用的训练模式的行数减少，通过移除用于临时存储训练模式的寄存器以及包括数据传输电路的半导体存储器件。 数据传输电路包括一个锁存单元和一个缓冲单元。 每当输入训练模式加载命令时，锁存单元将训练模式数据输入的一位与训练模式加载命令一起锁存。 响应于选通信号，缓冲器单元加载锁存在锁存单元中的多个位，包括一位训练模式数据。

    Semiconductor memory device for preventing mal-operation induced by misrecognizing addresses/data as commands and operating method thereof
    8.
    发明授权
    Semiconductor memory device for preventing mal-operation induced by misrecognizing addresses/data as commands and operating method thereof 失效
    半导体存储装置，用于防止误认识地址/数据引起的误操作作为命令及其操作方法

    公开(公告)号：US07944763B2

    公开(公告)日：2011-05-17

    申请号：US12488011

    申请日：2009-06-19

    申请人： Ji-Hyae Bae

    发明人： Ji-Hyae Bae

    IPC分类号： G11C7/00

    CPC分类号： G11C7/1078 ,  G11C7/109 ,  G11C7/22

    摘要： A semiconductor memory device and an operating method thereof prevent the mal-operation of the semiconductor memory device induced by misrecognizing addresses or data as commands. The semiconductor memory device includes a plurality of input pads, a data information path, a command path, a transfer block configured to transmit signals coupled through the input pads to the data information path and the command path, a command decoding block configured to decode signals transmitted through the command path to verify an inputting of a command, and a transmission control block configured to generate a control signal for controlling the signal transmission from the transfer block to the command path according to the verified result of the command decoding block.

    摘要翻译： 半导体存储器件及其操作方法防止由误认识地址或数据引起的半导体存储器件的误操作作为命令。 半导体存储器件包括多个输入焊盘，数据信息路径，命令路径，被配置为将通过输入焊盘耦合的信号传输到数据信息路径和命令路径的传输块，配置为对信号进行解码的命令解码块 通过命令路径发送以验证命令的输入;以及传输控制块，被配置为根据命令解码块的验证结果产生用于控制从传送块到命令路径的信号传输的控制信号。

    Semiconductor memory device
    10.
    发明授权
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US08144527B2

    公开(公告)日：2012-03-27

    申请号：US12005999

    申请日：2007-12-28

    申请人： Ji-Hyae Bae ,  Sang-Sik Yoon

    发明人： Ji-Hyae Bae ,  Sang-Sik Yoon

    IPC分类号： G11C7/00

    CPC分类号： G11C5/063 ,  G11C7/1066 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/4096 ,  G11C29/02 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028 ,  G11C2207/2254

    摘要： A semiconductor memory device includes: a data multiplexing unit configured to output one of a data training pattern and data transferred through a first global input/output line in response to a training control signal; and a latch unit configured to latch an output of the data multiplexing unit to apply and maintain the latched output to a second global input/output line.

    摘要翻译： 半导体存储器件包括：数据复用单元，被配置为响应于训练控制信号输出数据训练模式和通过第一全局输入/输出线传送的数据中的一个; 以及锁存单元，被配置为锁存数据复用单元的输出以将锁存的输出施加并保持到第二全局输入/输出线。