公开(公告)号：US08503239B2

公开(公告)日：2013-08-06

申请号：US12980267

申请日：2010-12-28

申请人： Jung Mi Tak ,  Ji Hyae Bae

发明人： Jung Mi Tak ,  Ji Hyae Bae

IPC分类号： G06F12/00 ,  G06F13/00

CPC分类号： G11C8/12 ,  G11C16/08

摘要： A block control device for a semiconductor memory and a method for controlling the same are disclosed, which relate to a technology for controlling a block operation state of a Low Power Double-Data-Rate 2 (LPDDR2) non-volatile memory device. A block control device for use in a semiconductor memory includes a block address comparator configured to compare a first block address with a last block address, and output a same pulse or unequal pulse according to the comparison result, a block address driver configured to output a lock state control signal for driving a block address in response to the same pulse, a block address counter configured to count block addresses from the first block address to the last block address in response to the unequal pulse, and generate a block data activation pulse, and a block address register configured to store a lock state of a corresponding block in response to the lock state control signal and the block data activation pulse.

摘要翻译： 公开了一种用于半导体存储器的块控制装置及其控制方法，其涉及用于控制低功率双数据速率2（LPDDR2）非易失性存储器件的块操作状态的技术。 一种用于半导体存储器的块控制装置，包括块地址比较器，被配置为将第一块地址与最后块地址进行比较，并根据比较结果输出相同的脉冲或不相等的脉冲;块地址驱动器，被配置为输出 锁定状态控制信号，用于响应于相同的脉冲驱动块地址;块地址计数器，被配置为响应于不等脉冲将块地址从第一块地址计数到最后块地址，并且生成块数据激活脉冲， 以及块地址寄存器，被配置为响应于锁定状态控制信号和块数据激活脉冲而存储相应块的锁定状态。

公开(公告)号：US08654603B2

公开(公告)日：2014-02-18

申请号：US13467954

申请日：2012-05-09

申请人： Jung Mi Tak ,  Ji Hyae Bae

发明人： Jung Mi Tak ,  Ji Hyae Bae

IPC分类号： G11C29/04

CPC分类号： G11C29/16 ,  G11C13/00

摘要： A nonvolatile memory device is provided relating to a test operation for a Low Power Double-Data-Rate (LPDDR) nonvolatile memory device. The nonvolatile memory device comprises a command decoder configured to decode a test mode signal in a test mode to output program and erasure signals into a memory, an address decoder configured to decode a command address inputted through an address pin in the test mode to output a cell array address into the memory, and an overlay window configured to store a data inputted through a data pin in the test mode.

摘要翻译： 提供了关于低功率双数据速率（LPDDR）非易失性存储器件的测试操作的非易失性存储器件。 非易失性存储器件包括：命令解码器，被配置为在测试模式下解码测试模式信号，以将程序和擦除信号输出到存储器中;地址解码器，被配置为对在测试模式中通过地址引脚输入的命令地址进行解码，以输出 单元阵列地址到存储器中，并且覆盖窗口被配置为存储在测试模式中通过数据引脚输入的数据。

公开(公告)号：US08300495B2

公开(公告)日：2012-10-30

申请号：US12983011

申请日：2010-12-31

申请人： Jung Mi Tak ,  Hyuck Soo Yoon ,  Ji Hyae Bae

发明人： Jung Mi Tak ,  Hyuck Soo Yoon ,  Ji Hyae Bae

IPC分类号： G11C8/00

CPC分类号： G11C7/22 ,  G11C7/20 ,  G11C16/22

摘要： A block control command generation circuit includes first and second latch units, an input selection unit, a pull-down driving unit, and an output selection unit. The first and second latch units store initial values at different levels in response to initialization signals. The input selection unit selectively transmits a first block control signal to the first latch unit in response to an input enable signal. The pull-down driving unit selectively pull-down drives an input node of the second latch unit in response to a second block control signal and the input enable signal. The output selection unit outputs signals, which are stored in the first and second latch units, as first and second block control command signals in response to an output enable signal, respectively.

摘要翻译： 块控制命令生成电路包括第一和第二锁存单元，输入选择单元，下拉驱动单元和输出选择单元。 第一和第二锁存单元响应初始化信号存储不同电平的初始值。 输入选择单元响应于输入使能信号选择性地向第一锁存单元发送第一块控制信号。 选择性地下拉的下拉驱动单元响应于第二块控制信号和输入使能信号驱动第二锁存单元的输入节点。 输出选择单元响应于输出使能信号分别输出存储在第一和第二锁存单元中的信号作为第一和第二块控制命令信号。

公开(公告)号：US08811097B2

公开(公告)日：2014-08-19

申请号：US13602006

申请日：2012-08-31

申请人： Ji Hyae Bae ,  Jung Mi Tak

发明人： Ji Hyae Bae ,  Jung Mi Tak

IPC分类号： G11C7/00

CPC分类号： G11C7/20 ,  G11C7/24 ,  G11C8/12 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0023 ,  G11C13/0059

摘要： A semiconductor device includes: a memory cell array comprising a plurality of blocks each comprising a memory cell arranged at an intersection between a word line and a bit line; and a block state information storing unit configured to store state information of the respective blocks. The block state information storing unit stores lock state information to partially limit access to each of the blocks in response to a power-up signal.

摘要翻译： 半导体器件包括：包括多个块的存储单元阵列，每个块包括布置在字线和位线之间的交叉点处的存储单元; 以及块状态信息存储单元，被配置为存储各个块的状态信息。 块状态信息存储单元存储锁定状态信息，以响应于上电信号来部分地限制对每个块的访问。

公开(公告)号：US20120137046A1

公开(公告)日：2012-05-31

申请号：US12980267

申请日：2010-12-28

申请人： Jung Mi TAK ,  Ji Hyae Bae

发明人： Jung Mi TAK ,  Ji Hyae Bae

IPC分类号： G06F1/04 ,  G06F12/00

CPC分类号： G11C8/12 ,  G11C16/08

摘要： A block control device for a semiconductor memory and a method for controlling the same are disclosed, which relate to a technology for controlling a block operation state of a Low Power Double-Data-Rate 2 (LPDDR2) non-volatile memory device. A block control device for use in a semiconductor memory includes a block address comparator configured to compare a first block address with a last block address, and output a same pulse or unequal pulse according to the comparison result, a block address driver configured to output a lock state control signal for driving a block address in response to the same pulse, a block address counter configured to count block addresses from the first block address to the last block address in response to the unequal pulse, and generate a block data activation pulse, and a block address register configured to store a lock state of a corresponding block in response to the lock state control signal and the block data activation pulse.

摘要翻译： 公开了一种用于半导体存储器的块控制装置及其控制方法，其涉及用于控制低功率双数据速率2（LPDDR2）非易失性存储器件的块操作状态的技术。 一种用于半导体存储器的块控制装置，包括块地址比较器，被配置为将第一块地址与最后块地址进行比较，并根据比较结果输出相同的脉冲或不相等的脉冲;块地址驱动器，被配置为输出 锁定状态控制信号，用于响应于相同的脉冲驱动块地址;块地址计数器，被配置为响应于不等脉冲将块地址从第一块地址计数到最后块地址，并且生成块数据激活脉冲， 以及块地址寄存器，被配置为响应于锁定状态控制信号和块数据激活脉冲而存储相应块的锁定状态。

公开(公告)号：US20080253203A1

公开(公告)日：2008-10-16

申请号：US12047793

申请日：2008-03-13

申请人： Ji Hyae Bae

发明人： Ji Hyae Bae

IPC分类号： G11C7/00 ,  G11C8/18

CPC分类号： G11C7/1051 ,  G11C7/1036 ,  G11C7/106

摘要： A data output circuit for a semiconductor memory apparatus includes a data output control unit that generates a selection signal, an output timing signal, and an input control signal in response to a read command and a clock, and a signal-responsive data output unit that receives parallel data in response to the input control signal, arranges the parallel data in response to the selection signal, and sequentially outputs the arranged parallel data as serial data in synchronization with the output timing signal.

摘要翻译： 一种用于半导体存储装置的数据输出电路，包括：数据输出控制单元，响应读取命令和时钟，产生选择信号，输出定时信号和输入控制信号;以及信号响应数据输出单元， 响应于输入控制信号接收并行数据，根据选择信号排列并行数据，并且与输出定时信号同步地顺序输出排列的并行数据作为串行数据。

公开(公告)号：US09042198B2

公开(公告)日：2015-05-26

申请号：US14020534

申请日：2013-09-06

申请人： Yutaka Shirai ,  Naoki Shimizu ,  Kenji Tsuchida ,  Yoji Watanabe ,  Ji Hyae Bae ,  Yong Ho Kim

发明人： Yutaka Shirai ,  Naoki Shimizu ,  Kenji Tsuchida ,  Yoji Watanabe ,  Ji Hyae Bae ,  Yong Ho Kim

IPC分类号： G11C8/00 ,  G11C7/12 ,  G11C8/10 ,  G11C8/12

CPC分类号： G11C7/12 ,  G11C7/1039 ,  G11C7/222 ,  G11C8/10 ,  G11C8/12 ,  G11C8/18 ,  G11C11/1653 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1693

摘要： According to one embodiment, a memory includes a memory cell array with banks, each bank including rows, a first word lines provided in corresponding to the rows, an address latch circuit which latches a first row address signal, a row decoder which activates one of the first word lines, and a control circuit which is configured to execute a first operation which activates one of the banks based on a bank address signal when a first command is loaded, and a second operation which latches the first row address signal in the address latch circuit, and execute a third operation which activates one of the first word lines by the row decoder based on a second row address signal and the first row address signal latched in the address latch circuit when a second command is loaded after the first command.

摘要翻译： 根据一个实施例，存储器包括具有存储体的存储单元阵列，每个存储体包括行，对应于行的第一字线，锁存第一行地址信号的地址锁存电路， 第一字线，以及控制电路，被配置为当加载第一命令时，基于存储体地址信号执行第一操作，该第一操作激活存储区中的一个存储体;以及第二操作，其将地址中的第一行地址信号锁存 并且执行第三操作，当在第一命令之后加载第二命令时，基于第二行地址信号和锁存在地址锁存电路中的第一行地址信号，由行解码器激活第一字线之一。

公开(公告)号：US09613671B2

公开(公告)日：2017-04-04

申请号：US14692239

申请日：2015-04-21

申请人： Yutaka Shirai ,  Naoki Shimizu ,  Kenji Tsuchida ,  Yoji Watanabe ,  Ji Hyae Bae ,  Yong Ho Kim

发明人： Yutaka Shirai ,  Naoki Shimizu ,  Kenji Tsuchida ,  Yoji Watanabe ,  Ji Hyae Bae ,  Yong Ho Kim

IPC分类号： G11C8/00 ,  G11C8/18 ,  G11C7/12 ,  G11C8/10 ,  G11C8/12 ,  G11C11/16 ,  G11C7/10

CPC分类号： G11C7/12 ,  G11C7/1039 ,  G11C7/222 ,  G11C8/10 ,  G11C8/12 ,  G11C8/18 ,  G11C11/1653 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1693

摘要： According to one embodiment, a memory includes a memory cell array with banks, each bank including rows, a first word lines provided in corresponding to the rows, an address latch circuit which latches a first row address signal, a row decoder which activates one of the first word lines, and a control circuit which is configured to execute a first operation which activates one of the banks based on a bank address signal when a first command is loaded, and a second operation which latches the first row address signal in the address latch circuit, and execute a third operation which activates one of the first word lines by the row decoder based on a second row address signal and the first row address signal latched in the address latch circuit when a second command is loaded after the first command.

公开(公告)号：US09530480B2

公开(公告)日：2016-12-27

申请号：US14864271

申请日：2015-09-24

申请人： Naoki Shimizu ,  Ji Hyae Bae

发明人： Naoki Shimizu ,  Ji Hyae Bae

IPC分类号： G11C11/16 ,  G11C13/00 ,  G11C7/22 ,  G11C11/4076 ,  G11C7/08 ,  G11C11/409 ,  G11C11/419 ,  G11C8/18 ,  G11C11/56 ,  G11C7/10 ,  G11C8/16

CPC分类号： G11C11/1693 ,  G11C7/08 ,  G11C7/109 ,  G11C7/22 ,  G11C7/222 ,  G11C8/16 ,  G11C8/18 ,  G11C11/1653 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/4076 ,  G11C11/419 ,  G11C11/5607 ,  G11C13/0023 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069

摘要： A semiconductor memory device is capable of executing a first mode having a first latency and a second mode having a second latency longer than the first latency. The semiconductor memory device includes: a pad unit configured to receive an address and a command from an outside; a first delay circuit configured to delay the address by a time corresponding to the first latency; a second delay circuit including shift registers connected in series and configured to delay the address by a time corresponding to a difference between the first latency and the second latency; and a controller configured to use the first delay circuit and the second delay circuit when executing the second mode.

公开(公告)号：US09171600B2

公开(公告)日：2015-10-27

申请号：US14201686

申请日：2014-03-07

申请人： Naoki Shimizu ,  Ji Hyae Bae

发明人： Naoki Shimizu ,  Ji Hyae Bae

IPC分类号： G11C11/16 ,  G11C13/00 ,  G11C7/22 ,  G11C11/4076 ,  G11C7/08 ,  G11C11/409 ,  G11C8/18 ,  G11C11/419 ,  G11C11/56 ,  G11C7/10

CPC分类号： G11C11/1693 ,  G11C7/08 ,  G11C7/109 ,  G11C7/22 ,  G11C7/222 ,  G11C8/16 ,  G11C8/18 ,  G11C11/1653 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/4076 ,  G11C11/419 ,  G11C11/5607 ,  G11C13/0023 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069

摘要： A semiconductor memory device is capable of executing a first mode having a first latency and a second mode having a second latency longer than the first latency. The semiconductor memory device includes: a pad unit configured to receive an address and a command from an outside; a first delay circuit configured to delay the address by a time corresponding to the first latency; a second delay circuit including shift registers connected in series and configured to delay the address by a time corresponding to a difference between the first latency and the second latency; and a controller configured to use the first delay circuit and the second delay circuit when executing the second mode.

摘要翻译： 半导体存储器件能够执行具有第一等待时间的第一模式和具有比第一等待时间长的第二等待时间的第二模式。 半导体存储器件包括：焊盘单元，被配置为从外部接收地址和命令; 第一延迟电路，被配置为将所述地址延迟与所述第一等待时间相对应的时间; 第二延迟电路，包括串联连接的移位寄存器，并配置为将地址延迟与第一等待时间和第二等待时间之间的差对应的时间; 以及控制器，被配置为在执行第二模式时使用第一延迟电路和第二延迟电路。