公开(公告)号：US20130115742A1

公开(公告)日：2013-05-09

申请号：US13495062

申请日：2012-06-13

申请人： Seok-Hoon KIM ,  Sang-Su KIM ,  Chung-Geun KOH ,  Sun-Ghil LEE ,  Jin-Yeong JOE

发明人： Seok-Hoon KIM ,  Sang-Su KIM ,  Chung-Geun KOH ,  Sun-Ghil LEE ,  Jin-Yeong JOE

IPC分类号： H01L21/336

CPC分类号： H01L29/7847 ,  H01L21/26506 ,  H01L21/26593 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/7843

摘要： The manufacturing a semiconductor device includes providing a substrate supporting a gate electrode, amorphizing and doping the source/drain regions located on both sides of the gate electrode by performing a pre-amorphization implant (PAI) process and implanting C or N into the source/drain regions in or separately from the PAI process, forming a stress inducing layer on the substrate to cover the amorphized source/drain regions, and subsequently recrystallizing the source/drain regions by annealing the substrate. The stress inducing layer may then be removed. Also, the C or N may be implanted into the entirety of the source/drain regions after the regions have been amorphized, or only into upper portions of the amorphized source/drain regions.

摘要翻译： 制造半导体器件包括提供支撑栅电极的衬底，通过执行预非晶化注入（PAI）工艺并且将C或N注入到源/漏区中来对位于栅电极的两侧的源/漏区进行非晶化和掺杂， 漏极区域或与PAI工艺分离，在衬底上形成应力诱导层以覆盖非晶化源极/漏极区域，并且随后通过对衬底退火来使源极/漏极区域再结晶。 然后可以去除应力诱导层。 此外，在区域已经非晶化之后，或仅仅在非晶化源极/漏极区域的上部，C或N可以被注入到整个源极/漏极区域中。

公开(公告)号：US09793356B2

公开(公告)日：2017-10-17

申请号：US14824057

申请日：2015-08-11

申请人： Jeong-Ho Yoo ,  Byeong-Chan Lee ,  Hyun-Ho Noh ,  Yong-Kook Park ,  Bon-Young Koo ,  Jin-Yeong Joe

发明人： Jeong-Ho Yoo ,  Byeong-Chan Lee ,  Hyun-Ho Noh ,  Yong-Kook Park ,  Bon-Young Koo ,  Jin-Yeong Joe

IPC分类号： H01L29/16 ,  H01L29/78 ,  H01L21/8238 ,  H01L21/84 ,  H01L29/66 ,  H01L27/092 ,  H01L27/12

CPC分类号： H01L29/1608 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

摘要： A semiconductor device may have a structure that prevents or reduces an etching amount of certain portions, such as a part of a source/drain region. Adjacent active fins may be merged with a blocking layer extending between adjacent the source/drain region. The blocking layer may be of a material that is relatively high-resistant to the etchant.

公开(公告)号：US20160079367A1

公开(公告)日：2016-03-17

申请号：US14824057

申请日：2015-08-11

申请人： Jeong-Ho YOO ,  Byeong-Chan LEE ,  Hyun-Ho NOH ,  Yong-Kook PARK ,  Bon-Young KOO ,  Jin-Yeong JOE

发明人： Jeong-Ho YOO ,  Byeong-Chan LEE ,  Hyun-Ho NOH ,  Yong-Kook PARK ,  Bon-Young KOO ,  Jin-Yeong JOE

IPC分类号： H01L29/10 ,  H01L29/16 ,  H01L29/06 ,  H01L29/167 ,  H01L29/165 ,  H01L29/78

CPC分类号： H01L29/1608 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

摘要： A semiconductor device may have a structure that prevents or reduces an etching amount of certain portions, such as a part of a source/drain region. Adjacent active fins may be merged with a blocking layer extending between adjacent the source/drain region. The blocking layer may be of a material that is relatively high-resistant to the etchant.

摘要翻译： 半导体器件可以具有防止或减少某些部分（例如源极/漏极区域的一部分）的蚀刻量的结构。 相邻的活性鳍片可以与在相邻的源极/漏极区域之间延伸的阻挡层合并。 阻挡层可以是相对于蚀刻剂相对高的材料。

公开(公告)号：US08772095B2

公开(公告)日：2014-07-08

申请号：US13495062

申请日：2012-06-13

申请人： Seok-Hoon Kim ,  Sang-Su Kim ,  Chung-Geun Koh ,  Sun-Ghil Lee ,  Jin-Yeong Joe

发明人： Seok-Hoon Kim ,  Sang-Su Kim ,  Chung-Geun Koh ,  Sun-Ghil Lee ,  Jin-Yeong Joe

IPC分类号： H01L21/00

CPC分类号： H01L29/7847 ,  H01L21/26506 ,  H01L21/26593 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/7843

摘要： The manufacturing a semiconductor device includes providing a substrate supporting a gate electrode, amorphizing and doping the source/drain regions located on both sides of the gate electrode by performing a pre-amorphization implant (PAI) process and implanting C or N into the source/drain regions in or separately from the PAI process, forming a stress inducing layer on the substrate to cover the amorphized source/drain regions, and subsequently recrystallizing the source/drain regions by annealing the substrate. The stress inducing layer may then be removed. Also, the C or N may be implanted into the entirety of the source/drain regions after the regions have been amorphized, or only into upper portions of the amorphized source/drain regions.

摘要翻译： 制造半导体器件包括提供支撑栅电极的衬底，通过执行预非晶化注入（PAI）工艺并且将C或N注入到源/漏区中来对位于栅电极的两侧的源/漏区进行非晶化和掺杂， 漏极区域或与PAI工艺分离，在衬底上形成应力诱导层以覆盖非晶化源极/漏极区域，并且随后通过对衬底退火来使源极/漏极区域再结晶。 然后可以去除应力诱导层。 此外，在区域已经非晶化之后，或仅仅在非晶化源极/漏极区域的上部，C或N可以被注入到整个源极/漏极区域中。