公开(公告)号：US08298926B2

公开(公告)日：2012-10-30

申请号：US12521268

申请日：2007-12-27

申请人： Hyung-Kook Park ,  Jin-Kyun Hong ,  Kun Kim ,  Chung-Geun Koh

发明人： Hyung-Kook Park ,  Jin-Kyun Hong ,  Kun Kim ,  Chung-Geun Koh

IPC分类号： H01L21/324 ,  C03B25/00

CPC分类号： H01L21/3225

摘要： A method for making a silicon wafer includes the steps of generating and stabilizing embryos that become oxygen precipitates by succeeding thermal annealing applied during a semiconductor device manufacturing process. In the silicon wafer, embryos are substantially removed in a denuded zone, and embryos are distributed at a relatively higher concentration in a bulk region. Also, by controlling behaviors of embryos, a silicon wafer having a desired concentration profile of oxygen precipitates by succeeding thermal annealing is manufactured with high reliability and reproducibility.

摘要翻译： 制造硅晶片的方法包括以下步骤：通过在半导体器件制造过程中施加的热退火，产生并稳定成为氧沉淀物的胚胎。 在硅晶片中，在裸露区域中基本上除去胚胎，并且在体积区域以相对较高的浓度分布胚胎。 此外，通过控制胚胎的行为，以高可靠性和再现性制造具有期望的热退火的氧析出物浓度分布的硅晶片。

公开(公告)号：US08101480B1

公开(公告)日：2012-01-24

申请号：US12944774

申请日：2010-11-12

申请人： Seok-Hoon Kim ,  Chung-Geun Koh ,  Kwan-Yong Lim ,  Hyun-Jung Lee ,  Tae-Ouk Kwon ,  Sang-Bom Kang

发明人： Seok-Hoon Kim ,  Chung-Geun Koh ,  Kwan-Yong Lim ,  Hyun-Jung Lee ,  Tae-Ouk Kwon ,  Sang-Bom Kang

IPC分类号： H01L21/8238 ,  H01L21/02

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L27/10873 ,  H01L27/10894 ,  H01L29/7848

摘要： A method of forming a transistor induces stress in the channel region using a stress memorization technique (SMT). Impurities are implanted into a substrate adjacent a gate electrode structure to produce an amorphous region adjacent the channel region. The amorphous region is then recrystallized by forming a metal-oxide layer over the amorphous region, and then thermally treating the same. The crystallization creates compressive stress in the amorphous region. As a result, stress is induced in the channel region of the substrate located under the gate electrode structure.

摘要翻译： 晶体管的形成方法利用应力记忆技术（SMT）在沟道区域中产生应力。 将杂质注入邻近栅电极结构的衬底中以产生邻近沟道区的非晶区。 然后通过在无定形区域上形成金属氧化物层使非晶区域重结晶，然后对其进行热处理。 结晶在非晶区域产生压应力。 结果，在位于栅电极结构下方的衬底的沟道区域中产生应力。

公开(公告)号：US20130115742A1

公开(公告)日：2013-05-09

申请号：US13495062

申请日：2012-06-13

申请人： Seok-Hoon KIM ,  Sang-Su KIM ,  Chung-Geun KOH ,  Sun-Ghil LEE ,  Jin-Yeong JOE

发明人： Seok-Hoon KIM ,  Sang-Su KIM ,  Chung-Geun KOH ,  Sun-Ghil LEE ,  Jin-Yeong JOE

IPC分类号： H01L21/336

CPC分类号： H01L29/7847 ,  H01L21/26506 ,  H01L21/26593 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/7843

摘要： The manufacturing a semiconductor device includes providing a substrate supporting a gate electrode, amorphizing and doping the source/drain regions located on both sides of the gate electrode by performing a pre-amorphization implant (PAI) process and implanting C or N into the source/drain regions in or separately from the PAI process, forming a stress inducing layer on the substrate to cover the amorphized source/drain regions, and subsequently recrystallizing the source/drain regions by annealing the substrate. The stress inducing layer may then be removed. Also, the C or N may be implanted into the entirety of the source/drain regions after the regions have been amorphized, or only into upper portions of the amorphized source/drain regions.

摘要翻译： 制造半导体器件包括提供支撑栅电极的衬底，通过执行预非晶化注入（PAI）工艺并且将C或N注入到源/漏区中来对位于栅电极的两侧的源/漏区进行非晶化和掺杂， 漏极区域或与PAI工艺分离，在衬底上形成应力诱导层以覆盖非晶化源极/漏极区域，并且随后通过对衬底退火来使源极/漏极区域再结晶。 然后可以去除应力诱导层。 此外，在区域已经非晶化之后，或仅仅在非晶化源极/漏极区域的上部，C或N可以被注入到整个源极/漏极区域中。

公开(公告)号：US08883651B2

公开(公告)日：2014-11-11

申请号：US13562826

申请日：2012-07-31

申请人： Seokhoon Kim ,  Sangsu Kim ,  Chung Geun Koh ,  Byeongchan Lee ,  Sunghil Lee ,  Jinyeong Joe

发明人： Seokhoon Kim ,  Sangsu Kim ,  Chung Geun Koh ,  Byeongchan Lee ,  Sunghil Lee ,  Jinyeong Joe

IPC分类号： H01L21/302 ,  H01L21/461 ,  H01L29/10 ,  H01L29/08 ,  H01L21/306 ,  H01L29/66 ,  H01L21/265 ,  H01L29/78 ,  H01L21/762 ,  H01L29/165 ,  H01L21/324

CPC分类号： H01L29/165 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/26593 ,  H01L21/30604 ,  H01L21/30608 ,  H01L21/324 ,  H01L21/76237 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66621 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7835 ,  H01L29/7848

摘要： A method of manufacturing a transistor of a semiconductor device, the method including forming a gate pattern on a semiconductor substrate, forming a spacer on a sidewall of the gate pattern, wet etching the semiconductor substrate to form a first recess in the semiconductor substrate, wherein the first recess is adjacent to the spacer, and wet etching the first recess to form a second recess in the semiconductor substrate.

摘要翻译： 一种制造半导体器件的晶体管的方法，所述方法包括在半导体衬底上形成栅极图案，在栅极图案的侧壁上形成间隔物，湿蚀刻半导体衬底以在半导体衬底中形成第一凹部，其中 所述第一凹部邻近所述间隔件，并且湿蚀刻所述第一凹部以在所述半导体衬底中形成第二凹部。

公开(公告)号：US08772095B2

公开(公告)日：2014-07-08

申请号：US13495062

申请日：2012-06-13

申请人： Seok-Hoon Kim ,  Sang-Su Kim ,  Chung-Geun Koh ,  Sun-Ghil Lee ,  Jin-Yeong Joe

发明人： Seok-Hoon Kim ,  Sang-Su Kim ,  Chung-Geun Koh ,  Sun-Ghil Lee ,  Jin-Yeong Joe

IPC分类号： H01L21/00

CPC分类号： H01L29/7847 ,  H01L21/26506 ,  H01L21/26593 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/7843

摘要： The manufacturing a semiconductor device includes providing a substrate supporting a gate electrode, amorphizing and doping the source/drain regions located on both sides of the gate electrode by performing a pre-amorphization implant (PAI) process and implanting C or N into the source/drain regions in or separately from the PAI process, forming a stress inducing layer on the substrate to cover the amorphized source/drain regions, and subsequently recrystallizing the source/drain regions by annealing the substrate. The stress inducing layer may then be removed. Also, the C or N may be implanted into the entirety of the source/drain regions after the regions have been amorphized, or only into upper portions of the amorphized source/drain regions.

摘要翻译： 制造半导体器件包括提供支撑栅电极的衬底，通过执行预非晶化注入（PAI）工艺并且将C或N注入到源/漏区中来对位于栅电极的两侧的源/漏区进行非晶化和掺杂， 漏极区域或与PAI工艺分离，在衬底上形成应力诱导层以覆盖非晶化源极/漏极区域，并且随后通过对衬底退火来使源极/漏极区域再结晶。 然后可以去除应力诱导层。 此外，在区域已经非晶化之后，或仅仅在非晶化源极/漏极区域的上部，C或N可以被注入到整个源极/漏极区域中。

公开(公告)号：US20120034749A1

公开(公告)日：2012-02-09

申请号：US13197658

申请日：2011-08-03

申请人： Kwan-Yong LIM ,  Chung-Geun Koh ,  Hyun-Jung Lee ,  Tae-Ouk Kwon ,  Seok-Hoon Kim ,  Tae-Ho Cha

发明人： Kwan-Yong LIM ,  Chung-Geun Koh ,  Hyun-Jung Lee ,  Tae-Ouk Kwon ,  Seok-Hoon Kim ,  Tae-Ho Cha

IPC分类号： H01L21/336

CPC分类号： H01L21/823412 ,  H01L21/823807 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7847

摘要： A method of manufacturing a semiconductor device can be provided by forming a gate structure on a substrate and forming a diffusion barrier layer on the gate structure and the substrate, A stress layer can be formed on the diffusion barrier layer comprising a metal nitride or a metal oxide having a concentration of nitrogen or oxygen associated therewith. The stress layer can be heated to transform the stress layer into a tensile stress layer to reduce the concentration of the nitrogen or the oxygen in the stress layer. The tensile stress layer and the diffusion barrier layer can be removed.

摘要翻译： 可以通过在衬底上形成栅极结构并在栅极结构和衬底上形成扩散阻挡层来提供制造半导体器件的方法.A应力层可以形成在包含金属氮化物或金属的扩散阻挡层上 具有与其相关联的氮或氧浓度的氧化物。 应力层可以被加热以将应力层转变成拉伸应力层，以减小应力层中的氮或氧的浓度。 可以去除拉伸应力层和扩散阻挡层。

公开(公告)号：US07732352B2

公开(公告)日：2010-06-08

申请号：US11765973

申请日：2007-06-20

申请人： Young Hee Mun ,  Kun Kim ,  Chung Geun Koh ,  Seung Ho Pyi

发明人： Young Hee Mun ,  Kun Kim ,  Chung Geun Koh ,  Seung Ho Pyi

IPC分类号： H01L21/324 ,  H01L21/322

CPC分类号： H01L21/324 ,  H01L21/3225

摘要： By using a two-step RTP (rapid thermal processing) process, the wafer is provided which has an ideal semiconductor device region secured by controlling fine oxygen precipitates and OiSFs (Oxidation Induced Stacking Fault) located on the surface region of the wafer. By performing the disclosed two-step rapid thermal process, the distribution of defects can be accurately controlled and an ideal device active zone can be formed up to a certain distance from the surfaces of the wafer. In addition, it is possible to maximize the internal gettering (IG) efficiency by enabling the oxygen precipitates and the bulk stacking faults to have constant densities in the depth direction in an internal region of the wafer, that is, the bulk region. In order to obtain the constant concentration profile of the oxygen precipitates and the bulk stacking faults in the bulk region, the wafer is subjected to the aforementioned two-step rapid thermal process in a predetermined mixed gas atmosphere.

摘要翻译： 通过使用两步RTP（快速热处理）工艺，提供晶片，其具有通过控制位于晶片表面区域上的精细氧沉淀物和OiSF（氧化诱导堆叠故障）而固定的理想半导体器件区域。 通过执行所公开的两步快速热处理，可以精确地控制缺陷的分布，并且可以形成理想的器件有源区至距离晶片表面一定距离。 此外，通过使晶体的内部区域即体积区域中的氧析出物和体积堆垛层错能够在深度方向上具有恒定的密度，可以使内部吸气（IG）效率最大化。 为了获得体积区域中的氧沉淀物的恒定浓度分布和体积堆垛层错，在预定的混合气体气氛中对晶片进行上述两步快速热处理。

公开(公告)号：US20100038755A1

公开(公告)日：2010-02-18

申请号：US12521268

申请日：2007-12-27

申请人： Hyung Kook Park ,  Jin-Kyun Hong ,  Kun Kim ,  Chung-Geun Koh

发明人： Hyung Kook Park ,  Jin-Kyun Hong ,  Kun Kim ,  Chung-Geun Koh

IPC分类号： H01L29/36 ,  H01L21/322

CPC分类号： H01L21/3225

摘要： A method for making a silicon wafer includes the steps of generating and stabilizing embryos that become oxygen precipitates by succeeding thermal annealing applied during a semiconductor device manufacturing process. In the silicon wafer, embryos are substantially removed in a denuded zone, and embryos are distributed at a relatively higher concentration in a bulk region. Also, by controlling behaviors of embryos, a silicon wafer having a desired concentration profile of oxygen precipitates by succeeding thermal annealing is manufactured with high reliability and reproducibility.

摘要翻译： 制造硅晶片的方法包括以下步骤：通过在半导体器件制造过程中施加的热退火，产生并稳定成为氧沉淀物的胚胎。 在硅晶片中，在裸露区域中基本上除去胚胎，并且在体积区域以相对较高的浓度分布胚胎。 此外，通过控制胚胎的行为，以高可靠性和再现性制造具有期望的热退火的氧析出物浓度分布的硅晶片。

公开(公告)号：US08633078B2

公开(公告)日：2014-01-21

申请号：US13240470

申请日：2011-09-22

申请人： Kwan-Yong Lim ,  Chung-Geun Koh ,  Sang-Bom Kang ,  Ui-Hui Kwon ,  Hyun-Jung Lee ,  Tae-Ouk Kwon ,  Seok-Hoon Kim

发明人： Kwan-Yong Lim ,  Chung-Geun Koh ,  Sang-Bom Kang ,  Ui-Hui Kwon ,  Hyun-Jung Lee ,  Tae-Ouk Kwon ,  Seok-Hoon Kim

IPC分类号： H01L21/336

CPC分类号： H01L29/66659 ,  H01L21/26506 ,  H01L21/26586 ,  H01L29/6659 ,  H01L29/7835 ,  H01L29/7847

摘要： A semiconductor device is formed with a gate pattern formed on a substrate, and a recrystallized region having a stacking fault defect in the substrate at one side of the gate pattern. The semiconductor device can have a reduced leakage current and improved channel conductivity.

摘要翻译： 半导体器件形成有形成在衬底上的栅极图案，以及在栅极图案一侧的衬底中具有层叠缺陷缺陷的再结晶区域。 半导体器件可以具有减小的漏电流和改善的沟道导电性。

公开(公告)号：US20130045589A1

公开(公告)日：2013-02-21

申请号：US13562826

申请日：2012-07-31

申请人： Seokhoon Kim ,  Sangsu Kim ,  Chung Geun Koh ,  Byeongchan Lee ,  Sunghil Lee ,  Jinyeong Joe

发明人： Seokhoon Kim ,  Sangsu Kim ,  Chung Geun Koh ,  Byeongchan Lee ,  Sunghil Lee ,  Jinyeong Joe

IPC分类号： H01L21/20 ,  H01L21/425

CPC分类号： H01L29/165 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/26593 ,  H01L21/30604 ,  H01L21/30608 ,  H01L21/324 ,  H01L21/76237 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/66621 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7835 ,  H01L29/7848

摘要： A method of manufacturing a transistor of a semiconductor device, the method including forming a gate pattern on a semiconductor substrate, forming a spacer on a sidewall of the gate pattern, wet etching the semiconductor substrate to form a first recess in the semiconductor substrate, wherein the first recess is adjacent to the spacer, and wet etching the first recess to form a second recess in the semiconductor substrate.

摘要翻译： 一种制造半导体器件的晶体管的方法，所述方法包括在半导体衬底上形成栅极图案，在栅极图案的侧壁上形成间隔物，湿蚀刻半导体衬底以在半导体衬底中形成第一凹部，其中 所述第一凹部邻近所述间隔件，并且湿蚀刻所述第一凹部以在所述半导体衬底中形成第二凹部。