公开(公告)号：US08772095B2

公开(公告)日：2014-07-08

申请号：US13495062

申请日：2012-06-13

申请人： Seok-Hoon Kim ,  Sang-Su Kim ,  Chung-Geun Koh ,  Sun-Ghil Lee ,  Jin-Yeong Joe

发明人： Seok-Hoon Kim ,  Sang-Su Kim ,  Chung-Geun Koh ,  Sun-Ghil Lee ,  Jin-Yeong Joe

IPC分类号： H01L21/00

CPC分类号： H01L29/7847 ,  H01L21/26506 ,  H01L21/26593 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/7843

摘要： The manufacturing a semiconductor device includes providing a substrate supporting a gate electrode, amorphizing and doping the source/drain regions located on both sides of the gate electrode by performing a pre-amorphization implant (PAI) process and implanting C or N into the source/drain regions in or separately from the PAI process, forming a stress inducing layer on the substrate to cover the amorphized source/drain regions, and subsequently recrystallizing the source/drain regions by annealing the substrate. The stress inducing layer may then be removed. Also, the C or N may be implanted into the entirety of the source/drain regions after the regions have been amorphized, or only into upper portions of the amorphized source/drain regions.

摘要翻译： 制造半导体器件包括提供支撑栅电极的衬底，通过执行预非晶化注入（PAI）工艺并且将C或N注入到源/漏区中来对位于栅电极的两侧的源/漏区进行非晶化和掺杂， 漏极区域或与PAI工艺分离，在衬底上形成应力诱导层以覆盖非晶化源极/漏极区域，并且随后通过对衬底退火来使源极/漏极区域再结晶。 然后可以去除应力诱导层。 此外，在区域已经非晶化之后，或仅仅在非晶化源极/漏极区域的上部，C或N可以被注入到整个源极/漏极区域中。

公开(公告)号：US09450049B2

公开(公告)日：2016-09-20

申请号：US14276421

申请日：2014-05-13

申请人： Tae-Yong Kwon ,  Sang-Su Kim ,  Jung-Gil Yang ,  Jung-Dal Choi

发明人： Tae-Yong Kwon ,  Sang-Su Kim ,  Jung-Gil Yang ,  Jung-Dal Choi

IPC分类号： H01L27/00 ,  H01L29/10 ,  H01L29/205 ,  H01L29/78 ,  H01L29/165 ,  H01L27/088 ,  H01L21/8238 ,  H01L21/84 ,  H01L29/66 ,  H01L27/092 ,  H01L27/12

CPC分类号： H01L29/1054 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/088 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/165 ,  H01L29/20 ,  H01L29/205 ,  H01L29/66522 ,  H01L29/6681 ,  H01L29/78 ,  H01L29/7842 ,  H01L29/785

摘要： A semiconductor device includes a substrate, a compound semiconductor layer, and first and second semiconductor patterns. The substrate includes first and second regions. The first semiconductor pattern is on the compound semiconductor layer of the first region and includes an element semiconductor. The second semiconductor pattern is on the compound semiconductor layer of the second region and includes a Group III-V semiconductor material.

摘要翻译： 半导体器件包括衬底，化合物半导体层以及第一和第二半导体图案。 衬底包括第一和第二区域。 第一半导体图案在第一区域的化合物半导体层上，并且包括元件半导体。 第二半导体图案在第二区域的化合物半导体层上，并且包括III-V族半导体材料。

公开(公告)号：US07170794B2

公开(公告)日：2007-01-30

申请号：US10971201

申请日：2004-10-21

申请人： Ki-Chul Kim ,  Byou-Ree Lim ,  Sang-Su Kim ,  Geum-Jong Bae ,  Kwang-Wook Koh

发明人： Ki-Chul Kim ,  Byou-Ree Lim ,  Sang-Su Kim ,  Geum-Jong Bae ,  Kwang-Wook Koh

IPC分类号： G11C11/34

CPC分类号： G11C16/0425

摘要： A programming method of a non-volatile memory device includes a pre-program of the non-volatile memory device, and a main-program of the pre-programmed non-volatile memory device. The non-volatile memory device may include a tunnel dielectric layer, a charge storage layer, a blocking dielectric layer, and a gate electrode, which are sequentially stacked on a semiconductor substrate. The charge storage layer may be an electrically-floated conductive layer, or a dielectric layer having a trap site. By performing a main-program after performing a pre-program, to increase the threshold voltage of the non-volatile memory device, the program current can be effectively reduced.

摘要翻译： 非易失性存储器件的编程方法包括非易失性存储器件的预编程以及预编程的非易失性存储器件的主程序。 非易失性存储器件可以包括依次堆叠在半导体衬底上的隧道介电层，电荷存储层，阻挡介电层和栅电极。 电荷存储层可以是具有陷阱位置的电浮动导电层或介电层。 通过在执行预编程之后执行主程序，为了增加非易失性存储器件的阈值电压，可以有效地减少编程电流。

公开(公告)号：US07045850B2

公开(公告)日：2006-05-16

申请号：US10844783

申请日：2004-05-13

申请人： Sang-Su Kim ,  Kwang-Wook Koh ,  Geum-Jong Bae ,  Ki-Chul Kim ,  Sung-Ho Kim ,  Jin-Hee Kim ,  In-Wook Cho

发明人： Sang-Su Kim ,  Kwang-Wook Koh ,  Geum-Jong Bae ,  Ki-Chul Kim ,  Sung-Ho Kim ,  Jin-Hee Kim ,  In-Wook Cho

IPC分类号： H01L29/76

CPC分类号： H01L27/11568 ,  H01L21/823462 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11546

摘要： The present invention discloses a semiconductor device having a floating trap type nonvolatile memory cell and a method for manufacturing the same. The method includes providing a semiconductor substrate having a nonvolatile memory region, a first region, and a second region. A triple layer composed of a tunnel oxide layer, a charge storing layer and a first deposited oxide layer on the semiconductor substrate is formed sequentially The triple layer on the semiconductor substrate except the nonvolatile memory region is then removed. A second deposited oxide layer is formed on an entire surface of the semiconductor substrate including the first and second regions from which the triple layer is removed. The second deposited oxide layer on the second region is removed, and a first thermal oxide layer is formed on the entire surface of the semiconductor substrate including the second region from which the second deposited oxide layer is removed. The semiconductor device can be manufactured according to the present invention to have a reduced processing time and a reduced change of impurity doping profile. The thickness of a blocking oxide layer and a high voltage gate oxide layer can be controlled.

摘要翻译： 本发明公开了一种具有浮动阱式非易失性存储单元的半导体器件及其制造方法。 该方法包括提供具有非易失性存储区域，第一区域和第二区域的半导体衬底。 依次形成由半导体衬底上的隧道氧化物层，电荷存储层和第一沉积氧化物层构成的三层，然后除去非易失性存储区域之外的半导体衬底上的三层。 第二沉积氧化物层形成在半导体衬底的包括去除三层的第一和第二区域的整个表面上。 去除第二区域上的第二沉积氧化物层，并且在包括除去第二沉积氧化物层的第二区域的半导体衬底的整个表面上形成第一热氧化物层。 可以根据本发明制造半导体器件以减少处理时间和降低杂质掺杂分布的变化。 可以控制阻挡氧化物层和高电压栅极氧化物层的厚度。

公开(公告)号：US20050186734A1

公开(公告)日：2005-08-25

申请号：US10786239

申请日：2004-02-24

申请人： In-Wook Cho ,  Nae-In Lee ,  Kwang-Wook Koh ,  Geun-Jong Bae ,  Sang-Su Kim ,  Jin-Hee Kim ,  Sung-Ho Kim ,  Ki-Chul Kim

发明人： In-Wook Cho ,  Nae-In Lee ,  Kwang-Wook Koh ,  Geun-Jong Bae ,  Sang-Su Kim ,  Jin-Hee Kim ,  Sung-Ho Kim ,  Ki-Chul Kim

IPC分类号： H01L27/10 ,  H01L21/336 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/115 ,  H01L27/11568 ,  Y10S438/954

摘要： A method of manufacturing a non-volatile semiconductor memory device begins by forming a dielectric layer pattern having an ONO composition on a substrate. A polysilicon layer is formed on the substrate including over the dielectric layer pattern. The polysilicon layer is patterned to form a split polysilicon layer pattern that exposes part of the dielectric layer pattern. The exposed dielectric layer is etched, and then impurities are implanted into portions of the substrate using the split polysilicon layer pattern as a mask to thereby form a source region having a vertical profile in the substrate.

摘要翻译： 制造非易失性半导体存储器件的方法是通过在衬底上形成具有ONO组成的电介质层图案而开始的。 在包括在电介质层图案上的衬底上形成多晶硅层。 图案化多晶硅层以形成暴露部分介电层图案的分裂多晶硅层图案。 暴露的电介质层被蚀刻，然后使用分离多晶硅层图案作为掩模将杂质注入到衬底的部分中，从而在衬底中形成具有垂直轮廓的源区。

公开(公告)号：US20050184334A1

公开(公告)日：2005-08-25

申请号：US11047764

申请日：2005-02-02

申请人： Ki-Chul Kim ,  Geum-Jong Bae ,  Byoung-jin Lee ,  Sang-Su Kim

发明人： Ki-Chul Kim ,  Geum-Jong Bae ,  Byoung-jin Lee ,  Sang-Su Kim

IPC分类号： H01L27/115 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8242 ,  H01L29/792

CPC分类号： H01L29/7923 ,  H01L21/28282 ,  H01L29/66833 ,  H01L29/792

摘要： A non-volatile memory device includes a pair of source/drain regions disposed in a semiconductor substrate, having a channel region between them. A charge storage oxide layer is disposed on the channel region and overlaps part of each of the pair of source/drain regions. A gate electrode is disposed on the charge storage oxide layer. At least one halo implantation region is formed in the semiconductor substrate adjacent to one of the pair of source/drain regions, and overlapping the charge storage oxide layer. A program operation is performed by trapping electrons in the charge storage oxide layer located near the source/drain region where the halo ion implantation region is formed, and an erase operation is performed by injecting holes into the charge storage oxide layer located near the source/drain region where the halo ion implantation region is formed.

摘要翻译： 非易失性存储器件包括设置在半导体衬底中的一对源极/漏极区域，它们之间具有沟道区域。 电荷存储氧化物层设置在沟道区上，并且与一对源极/漏极区的每一个的一部分重叠。 栅电极设置在电荷存储氧化物层上。 至少一个卤素注入区域形成在与一对源极/漏极区域中的一个相邻的半导体衬底中，并与电荷存储氧化物层重叠。 通过在位于形成有卤素离子注入区域的源极/漏极区附近的电荷存储氧化物层中俘获电子来执行编程操作，并且通过将空穴注入位于源/漏区附近的电荷存储氧化物层中来执行擦除操作， 漏区，其中形成有卤素离子注入区。

公开(公告)号：US20050088879A1

公开(公告)日：2005-04-28

申请号：US10971201

申请日：2004-10-21

申请人： Ki-Chul Kim ,  Byou-Ree Lim ,  Sang-Su Kim ,  Geum-Jong Bae ,  Kwang-Wook Koh

发明人： Ki-Chul Kim ,  Byou-Ree Lim ,  Sang-Su Kim ,  Geum-Jong Bae ,  Kwang-Wook Koh

IPC分类号： H01L27/115 ,  G11C16/04 ,  G11C11/34

CPC分类号： G11C16/0425

摘要： A programming method of a non-volatile memory device includes a pre-program of the non-volatile memory device, and a main-program of the pre-programmed non-volatile memory device. The non-volatile memory device may include a tunnel dielectric layer, a charge storage layer, a blocking dielectric layer, and a gate electrode, which are sequentially stacked on a semiconductor substrate. The charge storage layer may be an electrically-floated conductive layer, or a dielectric layer having a trap site. By performing a main-program after performing a pre-program, to increase the threshold voltage of the non-volatile memory device, the program current can be effectively reduced.

摘要翻译： 非易失性存储器件的编程方法包括非易失性存储器件的预编程以及预编程的非易失性存储器件的主程序。 非易失性存储器件可以包括依次堆叠在半导体衬底上的隧道介电层，电荷存储层，阻挡介电层和栅电极。 电荷存储层可以是具有陷阱位置的电浮动导电层或介电层。 通过在执行预编程之后执行主程序，为了增加非易失性存储器件的阈值电压，可以有效地减少编程电流。

公开(公告)号：US06794306B2

公开(公告)日：2004-09-21

申请号：US10463554

申请日：2003-06-17

申请人： Sang-Su Kim ,  Tae-Hee Choe ,  Hwa-Sung Rhee ,  Geum-Jong Bae ,  Nae-In Lee

发明人： Sang-Su Kim ,  Tae-Hee Choe ,  Hwa-Sung Rhee ,  Geum-Jong Bae ,  Nae-In Lee

IPC分类号： H01L2100

CPC分类号： H01L29/78696 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/66772 ,  H01L29/78654 ,  Y10S438/933

摘要： A semiconductor device having a transistor of gate all around (GAA) type and a method of fabricating the same are disclosed. A SOI substrate composed of a SOI layer, a buried oxide layer and a lower substrate is prepared. The SOI layer has at least one unit dual layer of a silicon germanium layer and a silicon layer. The SOI layer is patterned to form an active layer pattern to a certain direction. An insulation layer is formed to cover the active layer pattern. An etch stop layer is stacked on the active layer pattern covered with the insulation layer. The etch stop layer is patterned and removed at a gate region crossing the active layer pattern at the channel region. The insulation layer is removed at the gate region. The silicon germanium layer is isotropically etched and selectively removed to form a cavity at the channel region of the active layer pattern. In the state that the silicon germanium layer is selectively removed, a gate insulation layer is formed to cover the exposed surface of the active layer pattern. A gate conductivity layer is stacked on the substrate by a chemical vapor deposition (CVD) to fill the gate region including the cavity. The middle part of the channel region of the active layer pattern can be patterned to be divided by multiple patterns that are formed in a line.

摘要翻译： 公开了具有栅极全部（GAA）型晶体管的半导体器件及其制造方法。 制备由SOI层，掩埋氧化物层和下基板构成的SOI衬底。 SOI层具有硅锗层和硅层的至少一个单元双层。 图案化SOI层，以形成一定方向的有源层图案。 形成绝缘层以覆盖有源层图案。 在覆盖有绝缘层的有源层图案上堆叠蚀刻停止层。 蚀刻停止层被图案化并在沟道区域与有源层图案交叉的栅极区域去除。 绝缘层在栅极区域被去除。 硅锗层被各向同性地蚀刻并选择性地去除以在有源层图案的沟道区域形成空腔。 在选择性地去除硅锗层的状态下，形成栅极绝缘层以覆盖有源层图案的暴露表面。 通过化学气相沉积（CVD）将栅极导电层层叠在基板上，以填充包括空腔的栅极区域。 有源层图案的沟道区域的中间部分可以被图案化以被划分成一行形成的多个图案。

公开(公告)号：US06693013B2

公开(公告)日：2004-02-17

申请号：US10103759

申请日：2002-03-25

申请人： Geum-Jong Bae ,  Nae-In Lee ,  Hwa-Sung Rhee ,  Young-Gun Ko ,  Tae-Hee Choe ,  Sang-Su Kim

发明人： Geum-Jong Bae ,  Nae-In Lee ,  Hwa-Sung Rhee ,  Young-Gun Ko ,  Tae-Hee Choe ,  Sang-Su Kim

IPC分类号： H01L21336

CPC分类号： H01L29/66598 ,  H01L29/66507 ,  H01L29/66515 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659

摘要： The present invention provides a semiconductor transistor using an L-shaped spacer and a method of fabricating the same. The semiconductor transistor includes a gate pattern formed on a semiconductor substrate and an L-shaped third spacer formed beside the gate pattern and having a horizontal protruding portion. An L-shaped fourth spacer is formed between the third spacer and the gate pattern, and between the third spacer and the substrate. A high-concentration junction area is positioned in the substrate beyond the third spacer, and a low-concentration junction area is positioned under the horizontal protruding portion of the third spacer. A medium-concentration junction area is positioned between the high- and low-concentration junction areas. A method of fabricating the semiconductor transistor includes a process, where the high- and medium-concentration junction areas are formed simultaneously by the same ion-implantation step and the substrate is annealed before forming the low-concentration junction area.

摘要翻译： 本发明提供一种使用L形间隔物的半导体晶体管及其制造方法。 半导体晶体管包括形成在半导体衬底上的栅极图案和形成在栅极图案旁边并具有水平突出部分的L形第三间隔物。 在第三间隔物和栅极图案之间以及在第三间隔物和基底之间形成L形的第四间隔物。 高浓度接合区域位于第三间隔物之外的基板中，并且低浓度接合区域位于第三间隔物的水平突出部分的下方。 中等浓度接合区域位于高浓度和低浓度接合区域之间。 制造半导体晶体管的方法包括一个过程，其中通过相同的离子注入步骤同时形成高浓度和中等浓度的结区，并且在形成低浓度结区之前将衬底退火。

公开(公告)号：US06605847B2

公开(公告)日：2003-08-12

申请号：US10039151

申请日：2002-01-03

申请人： Sang-Su Kim ,  Tae-Hee Choe ,  Hwa-Sung Rhee ,  Geum-Jong Bae ,  Nae-In Lee

发明人： Sang-Su Kim ,  Tae-Hee Choe ,  Hwa-Sung Rhee ,  Geum-Jong Bae ,  Nae-In Lee

IPC分类号： H01L29786

CPC分类号： H01L29/78696 ,  H01L29/42384 ,  H01L29/42392 ,  H01L29/66772 ,  H01L29/78654 ,  Y10S438/933

摘要： A semiconductor device having a transistor of gate all around (GAA) type and a method of fabricating the same are disclosed. A SOI substrate composed of a SOI layer, a buried oxide layer and a lower substrate is prepared. The SOI layer has at least one unit dual layer of a silicon germanium layer and a silicon layer. The SOI layer is patterned to form an active layer pattern to a certain direction. An insulation layer is formed to cover the active layer pattern. An etch stop layer is stacked on the active layer pattern covered with the insulation layer. The etch stop layer is patterned and removed at a gate region crossing the active layer pattern at the channel region. The insulation layer is removed at the gate region. The silicon germanium layer is isotropically etched and selectively removed to form a cavity at the channel region of the active layer pattern. In the state that the silicon germanium layer is selectively removed, a gate insulation layer is formed to cover the exposed surface of the active layer pattern. A gate conductivity layer is stacked on the substrate by a chemical vapor deposition (CVD) to fill the gate region including the cavity. The middle part of the channel region of the active layer pattern can be patterned to be divided by multiple patterns that are formed in a line.