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    Semiconductor Devices Having Source/Drain Regions with Strain-Inducing Layers and Methods of Manufacturing Such Semiconductor Devices
    5.
    发明申请
    Semiconductor Devices Having Source/Drain Regions with Strain-Inducing Layers and Methods of Manufacturing Such Semiconductor Devices 有权
    具有应变诱导层的源极/漏极区域的半导体器件以及制造这种半导体器件的方法

    公开(公告)号：US20160027875A1

    公开(公告)日：2016-01-28

    申请号：US14680458

    申请日：2015-04-07

    Applicant: Seok-hoon Kim ,  Jin-bum Kim ,  Kwan-heum Lee ,  Byeong-chan Lee ,  Cho-eun Lee ,  Su-jin Jung

    Inventor： Seok-hoon Kim ,  Jin-bum Kim ,  Kwan-heum Lee ,  Byeong-chan Lee ,  Cho-eun Lee ,  Su-jin Jung

    IPC: H01L29/10 ,  H01L29/78

    CPC classification number: H01L29/7848 ,  H01L21/02236 ,  H01L21/02255 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/1033 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/7831 ,  H01L29/785 ,  H01L29/7851 ,  H01L29/7856

    Abstract: Semiconductor devices include a strain-inducing layer capable of applying a strain to a channel region of a transistor included in a miniaturized electronic device, and a method of manufacturing the semiconductor device. The semiconductor device includes a substrate having a channel region; a pair of source/drain regions provided on the substrate and arranged on both sides of the channel region in a first direction; and a gate structure provided on the channel region and comprising a gate electrode pattern extending in a second direction that is different from the first direction, a gate dielectric layer disposed between the channel region and the gate electrode pattern, and a gate spacer covering respective lateral surfaces of the gate electrode pattern and the gate dielectric layer. At least one of the source/drain regions includes a first strain-inducing layer and a second strain-inducing layer. The first strain-inducing layer is disposed between a lateral surface of the channel region and the second strain-inducing layer and contacts at least a portion of the gate dielectric layer.

    Abstract translation: 半导体器件包括能够对包括在小型化电子器件中的晶体管的沟道区域施加应变的应变诱导层以及半导体器件的制造方法。 半导体器件包括具有沟道区的衬底; 一对源极/漏极区，设置在所述衬底上并沿第一方向布置在所述沟道区的两侧; 以及栅极结构，设置在所述沟道区上并且包括在与所述第一方向不同的第二方向上延伸的栅极电极图案，设置在所述沟道区域和所述栅极电极图案之间的栅极介电层以及覆盖相应侧面的栅极间隔件 栅电极图案和栅介质层的表面。 源极/漏极区域中的至少一个包括第一应变诱导层和第二应变诱导层。 第一应变诱导层设置在沟道区的侧表面和第二应变诱导层之间，并与栅介质层的至少一部分接触。

    Methods of fabricating MOS transistors having recesses with elevated source/drain regions
    7.
    发明授权
    Methods of fabricating MOS transistors having recesses with elevated source/drain regions 有权
    制造具有升高的源极/漏极区域的凹槽的MOS晶体管的方法

    公开(公告)号：US08304318B2

    公开(公告)日：2012-11-06

    申请号：US13241311

    申请日：2011-09-23

    Applicant: Yong-Hoon Son ,  Si-Young Choi ,  Byeong-Chan Lee ,  Deok-Hyung Lee ,  In-Soo Jung

    Inventor： Yong-Hoon Son ,  Si-Young Choi ,  Byeong-Chan Lee ,  Deok-Hyung Lee ,  In-Soo Jung

    IPC: H01L21/336

    CPC classification number: H01L29/6659 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/7833

    Abstract: Methods of fabricating metal-oxide-semiconductor (MOS) transistors having elevated source/drain regions are provided. The MOS transistors formed by these methods may include a gate pattern formed to cross over a predetermined region of a substrate. Recessed regions are provided in the substrate adjacent to the gate pattern. Epitaxial layers are provided on bottom surfaces of the recessed regions. High concentration impurity regions are provided in the epitaxial layers. The recessed regions may be formed using a chemical dry etching techniques.

    Abstract translation: 提供了具有升高的源极/漏极区域的金属氧化物半导体（MOS）晶体管的制造方法。 通过这些方法形成的MOS晶体管可以包括形成为跨越衬底的预定区域的栅极图案。 凹陷区域设置在与栅极图案相邻的衬底中。 外凹层设置在凹陷区域的底表面上。 在外延层中设置高浓度杂质区。 凹陷区域可以使用化学干蚀刻技术形成。

    Semiconductor memory devices having vertical channel transistors and related methods
    10.
    发明授权
    Semiconductor memory devices having vertical channel transistors and related methods 有权
    具有垂直沟道晶体管的半导体存储器件及相关方法

    公开(公告)号：US08008698B2

    公开(公告)日：2011-08-30

    申请号：US12198266

    申请日：2008-08-26

    Applicant: Deok-hyung Lee ,  Sun-ghil Lee ,  Si-young Choi ,  Byeong-chan Lee ,  Seung-hun Lee

    Inventor： Deok-hyung Lee ,  Sun-ghil Lee ,  Si-young Choi ,  Byeong-chan Lee ,  Seung-hun Lee

    IPC: H01L27/108

    CPC classification number: H01L27/10894 ,  H01L27/0207 ,  H01L27/10876 ,  H01L27/10882 ,  H01L27/10885

    Abstract: A semiconductor memory device may include a semiconductor substrate with an active region extending in a first direction parallel with respect to a surface of the semiconductor substrate. A pillar may extend from the active region in a direction perpendicular with respect to the surface of the semiconductor substrate with the pillar including a channel region on a sidewall thereof. A gate insulating layer may surround a sidewall of the pillar, and a word line may extend in a second direction parallel with respect to the surface of the semiconductor substrate. Moreover, the first and second directions may be different, and the word line may surround the sidewall of the pillar so that the gate insulating layer is between the word line and the pillar. A contact plug may be electrically connected to the active region and spaced apart from the word line, and a bit line may be electrically connected to the active region through the contact plug with the plurality of bit lines extending in the first direction. Related methods are also discussed.

    Abstract translation: 半导体存储器件可以包括具有在相对于半导体衬底的表面平行的第一方向上延伸的有源区的半导体衬底。 柱可以在与半导体衬底的表面垂直的方向上从有源区延伸，其中柱在其侧壁上包括沟道区。 栅极绝缘层可以围绕柱的侧壁，并且字线可以在相对于半导体衬底的表面平行的第二方向上延伸。 此外，第一和第二方向可以不同，并且字线可以围绕柱的侧壁，使得栅极绝缘层在字线和柱之间。 接触插塞可以电连接到有源区并与字线间隔开，并且位线可以通过接触插塞电连接到有源区，多个位线沿第一方向延伸。 还讨论了相关方法。

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