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    SEMICONDUCTOR DEVICE, SYSTEMS AND METHODS OF MANUFACTURE
    4.
    发明申请
    SEMICONDUCTOR DEVICE, SYSTEMS AND METHODS OF MANUFACTURE 审中-公开
    半导体器件，系统和制造方法

    公开(公告)号：US20150060992A1

    公开(公告)日：2015-03-05

    申请号：US14474867

    申请日：2014-09-02

    申请人： KIM TAEKYUNG ,  KWANG SOO SEOL ,  SEONG SOON CHO ,  SUNGHOI HUR ,  JINTAE KANG

    发明人： KIM TAEKYUNG ,  KWANG SOO SEOL ,  SEONG SOON CHO ,  SUNGHOI HUR ,  JINTAE KANG

    IPC分类号： H01L27/115

    CPC分类号： H01L27/1157 ,  H01L27/11519 ,  H01L27/11582 ,  H01L29/4234 ,  H01L29/7926

    摘要： A semiconductor memory device includes a stack of word lines and insulating patterns. Cell pillars extend vertically through the stack of word lines and insulating patterns with memory cells being formed at the junctions of the cell pillars and the word lines. A ratio of the thickness of the word lines to the thickness of immediately neighboring insulating patterns is different at different locations along one or more of the cell pillars. Related methods of manufacturing and systems are also disclosed.

    摘要翻译： 半导体存储器件包括字线和绝缘图案的堆叠。 单元柱垂直延伸穿过字线堆叠和绝缘图案，其中存储单元形成在单元柱和字线的交点处。 字线的厚度与紧邻绝缘图案的厚度的比例在沿着一个或多个单元柱的不同位置是不同的。 还公开了制造和系统的相关方法。

    MEMORY DEVICE
    8.
    发明申请
    MEMORY DEVICE 有权
    内存设备

    公开(公告)号：US20150054058A1

    公开(公告)日：2015-02-26

    申请号：US14530638

    申请日：2014-10-31

    申请人： Kwang Soo Seol ,  JinTae Kang ,  Seong Soon Cho

    发明人： Kwang Soo Seol ,  JinTae Kang ,  Seong Soon Cho

    IPC分类号： H01L27/115 ,  H01L29/792

    CPC分类号： H01L27/11582 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11573 ,  H01L29/0676 ,  H01L29/413 ,  H01L29/42332 ,  H01L29/66825 ,  H01L29/7889 ,  H01L29/7926

    摘要： Provided is a memory device including first to third selection lines extending in a first direction and sequentially arranged in a second direction crossing the first direction, multiple sets of first to third vertical pillars, each set coupled with a corresponding one of the first to third selection lines and sequentially arranged in the second direction, a first sub-interconnection connecting the third vertical pillar coupled with the first selection line to the first vertical pillar coupled with the second selection line, a second sub-interconnection connecting the third vertical pillar coupled with the second selection line to the first vertical pillar coupled with the third selection line, and bit lines extending in the second direction and connected to corresponding ones of the first and second sub-interconnections.

    摘要翻译： 提供了一种存储装置，包括：沿第一方向延伸的第一至第三选择线，并且沿与第一方向交叉的第二方向依次布置;多组第一至第三垂直柱，每组选择与第一至第三选择对应的一个组合 并且顺序地布置在第二方向上，将与第一选择线耦合的第三垂直柱连接到与第二选择线耦合的第一垂直柱的第一子互连，连接与第二选择线耦合的第三垂直柱的第二子互连 与第三选择线耦合的第一垂直柱的第二选择线，以及沿第二方向延伸并连接到第一和第二子互连中的对应的位线的位线。